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oops - wrong bit (vic zandy)

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rsc 2007-12-20 18:27:07 +00:00
parent c2258bf4d2
commit eadbd55af2
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ioapic.c
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@ -17,7 +17,7 @@
// The first (low) register in a pair contains configuration bits.
// The second (high) register contains a bitmask telling which
// CPUs can serve that interrupt.
#define INT_DISABLED 0x00100000 // Interrupt disabled
#define INT_DISABLED 0x00010000 // Interrupt disabled
#define INT_LEVEL 0x00008000 // Level-triggered (vs edge-)
#define INT_ACTIVELOW 0x00002000 // Active low (vs high)
#define INT_LOGICAL 0x00000800 // Destination is CPU id (vs APIC ID)