Simplify MP hardware code.
Mainly delete unused constants and code. Move mp_startthem to main.c as bootothers.
This commit is contained in:
rsc
parent
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commit
99b11b6c64
6 changed files with 213 additions and 453 deletions
97
ioapic.c
97
ioapic.c
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@ -1,85 +1,82 @@
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// The I/O APIC manages hardware interrupts for an SMP system.
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// http://www.intel.com/design/chipsets/datashts/29056601.pdf
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#include "types.h"
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#include "mp.h"
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#include "defs.h"
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#include "x86.h"
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#include "traps.h"
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#include "ioapic.h"
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#define IOAPIC 0xFEC00000 // Default physical address of IO APIC
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#define REG_ID 0x00 // Register index: ID
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#define REG_VER 0x01 // Register index: version
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#define REG_TABLE 0x10 // Redirection table base
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// The redirection table starts at REG_TABLE and uses
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// two registers to configure each interrupt.
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// The first (low) register in a pair contains configuration bits.
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// The second (high) register contains a bitmask telling which
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// CPUs can serve that interrupt.
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#define INT_DISABLED 0x00100000 // Interrupt disabled
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#define INT_LEVEL 0x00008000 // Level-triggered (vs edge-)
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#define INT_ACTIVELOW 0x00002000 // Active low (vs high)
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#define INT_LOGICAL 0x00000800 // Destination is CPU id (vs APIC ID)
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volatile struct ioapic *ioapic;
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// IO APIC MMIO structure: write reg, then read or write data.
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struct ioapic {
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uint ioregsel; uint p01; uint p02; uint p03;
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uint iowin; uint p11; uint p12; uint p13;
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uint reg;
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uint pad[3];
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uint data;
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};
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#define IOAPIC_REDTBL_LO(i) (IOAPIC_REDTBL + (i) * 2)
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#define IOAPIC_REDTBL_HI(i) (IOAPIC_REDTBL_LO(i) + 1)
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static uint
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ioapic_read(struct ioapic *io, int reg)
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ioapic_read(int reg)
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{
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io->ioregsel = reg;
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return io->iowin;
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ioapic->reg = reg;
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return ioapic->data;
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}
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static void
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ioapic_write(struct ioapic *io, int reg, uint val)
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ioapic_write(int reg, uint data)
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{
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io->ioregsel = reg;
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io->iowin = val;
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ioapic->reg = reg;
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ioapic->data = data;
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}
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void
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ioapic_init(void)
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{
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struct ioapic *io;
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uint l, h;
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int nintr;
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uchar id;
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int i;
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int i, id, maxintr;
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if(!ismp)
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return;
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io = (struct ioapic*) IO_APIC_BASE;
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l = ioapic_read(io, IOAPIC_VER);
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nintr = ((l & IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) + 1;
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id = ioapic_read(io, IOAPIC_ID) >> APIC_ID_SHIFT;
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ioapic = (volatile struct ioapic*)IOAPIC;
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maxintr = (ioapic_read(REG_VER) >> 16) & 0xFF;
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id = ioapic_read(REG_ID) >> 24;
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if(id != ioapic_id)
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cprintf("ioapic_init: id isn't equal to ioapic_id; not a MP\n");
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for(i = 0; i < nintr; i++) {
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// active-hi and edge-triggered for ISA interrupts
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// Assume that pin 0 on the first I/O APIC is an ExtINT pin.
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// Assume that pins 1-15 are ISA interrupts
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l = ioapic_read(io, IOAPIC_REDTBL_LO(i));
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l = l & ~IOART_INTMASK; // allow INTs
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l |= IOART_INTMSET;
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l = l & ~IOART_INTPOL; // active hi
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l = l & ~IOART_TRGRMOD; // edgee triggered
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l = l & ~IOART_DELMOD; // fixed
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l = l & ~IOART_DESTMOD; // physical mode
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l = l | (IRQ_OFFSET + i); // vector
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ioapic_write(io, IOAPIC_REDTBL_LO(i), l);
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h = ioapic_read(io, IOAPIC_REDTBL_HI(i));
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h &= ~IOART_DEST;
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ioapic_write(io, IOAPIC_REDTBL_HI(i), h);
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// Mark all interrupts edge-triggered, active high, disabled,
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// and not routed to any CPUs.
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for(i = 0; i <= maxintr; i++){
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ioapic_write(REG_TABLE+2*i, INT_DISABLED | (IRQ_OFFSET + i));
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ioapic_write(REG_TABLE+2*i+1, 0);
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}
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}
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void
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ioapic_enable (int irq, int cpunum)
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ioapic_enable(int irq, int cpunum)
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{
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uint l, h;
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struct ioapic *io;
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if(!ismp)
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return;
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io = (struct ioapic*) IO_APIC_BASE;
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l = ioapic_read(io, IOAPIC_REDTBL_LO(irq));
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l = l & ~IOART_INTMASK; // allow INTs
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ioapic_write(io, IOAPIC_REDTBL_LO(irq), l);
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h = ioapic_read(io, IOAPIC_REDTBL_HI(irq));
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h &= ~IOART_DEST;
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h |= (cpunum << APIC_ID_SHIFT);
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ioapic_write(io, IOAPIC_REDTBL_HI(irq), h);
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// Mark interrupt edge-triggered, active high,
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// enabled, and routed to the given cpunum,
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// which happens to be that cpu's APIC ID.
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ioapic_write(REG_TABLE+2*irq, IRQ_OFFSET + irq);
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ioapic_write(REG_TABLE+2*irq+1, cpunum << 24);
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}
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88
ioapic.h
88
ioapic.h
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@ -1,88 +0,0 @@
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#define IO_APIC_BASE 0xFEC00000 // Default phys addr of IO APIC
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#define IOAPIC_WINDOW 0x10 // Window register offset
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// Constants relating to APIC ID registers
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#define APIC_ID_MASK 0xff000000
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#define APIC_ID_SHIFT 24
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#define APIC_ID_CLUSTER 0xf0
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#define APIC_ID_CLUSTER_ID 0x0f
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#define APIC_MAX_CLUSTER 0xe
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#define APIC_MAX_INTRACLUSTER_ID 3
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#define APIC_ID_CLUSTER_SHIFT 4
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// Fields in VER
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#define APIC_VER_VERSION 0x000000ff
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#define APIC_VER_MAXLVT 0x00ff0000
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#define MAXLVTSHIFT 16
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// Indexes into IO APIC
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#define IOAPIC_ID 0x00
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#define IOAPIC_VER 0x01
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#define IOAPIC_ARB 0x02
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#define IOAPIC_REDTBL 0x10
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#define IOAPIC_REDTBL0 IOAPIC_REDTBL
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#define IOAPIC_REDTBL1 (IOAPIC_REDTBL+0x02)
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#define IOAPIC_REDTBL2 (IOAPIC_REDTBL+0x04)
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#define IOAPIC_REDTBL3 (IOAPIC_REDTBL+0x06)
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#define IOAPIC_REDTBL4 (IOAPIC_REDTBL+0x08)
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#define IOAPIC_REDTBL5 (IOAPIC_REDTBL+0x0a)
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#define IOAPIC_REDTBL6 (IOAPIC_REDTBL+0x0c)
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#define IOAPIC_REDTBL7 (IOAPIC_REDTBL+0x0e)
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#define IOAPIC_REDTBL8 (IOAPIC_REDTBL+0x10)
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#define IOAPIC_REDTBL9 (IOAPIC_REDTBL+0x12)
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#define IOAPIC_REDTBL10 (IOAPIC_REDTBL+0x14)
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#define IOAPIC_REDTBL11 (IOAPIC_REDTBL+0x16)
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#define IOAPIC_REDTBL12 (IOAPIC_REDTBL+0x18)
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#define IOAPIC_REDTBL13 (IOAPIC_REDTBL+0x1a)
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#define IOAPIC_REDTBL14 (IOAPIC_REDTBL+0x1c)
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#define IOAPIC_REDTBL15 (IOAPIC_REDTBL+0x1e)
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#define IOAPIC_REDTBL16 (IOAPIC_REDTBL+0x20)
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#define IOAPIC_REDTBL17 (IOAPIC_REDTBL+0x22)
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#define IOAPIC_REDTBL18 (IOAPIC_REDTBL+0x24)
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#define IOAPIC_REDTBL19 (IOAPIC_REDTBL+0x26)
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#define IOAPIC_REDTBL20 (IOAPIC_REDTBL+0x28)
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#define IOAPIC_REDTBL21 (IOAPIC_REDTBL+0x2a)
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#define IOAPIC_REDTBL22 (IOAPIC_REDTBL+0x2c)
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#define IOAPIC_REDTBL23 (IOAPIC_REDTBL+0x2e)
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// Fields in the IO APIC's redirection table entries
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#define IOART_DEST APIC_ID_MASK // broadcast addr: all APICs
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#define IOART_RESV 0x00fe0000 // reserved
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#define IOART_INTMASK 0x00010000 // R/W: INTerrupt mask
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#define IOART_INTMCLR 0x00000000 // clear, allow INTs
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#define IOART_INTMSET 0x00010000 // set, inhibit INTs
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#define IOART_TRGRMOD 0x00008000 // R/W: trigger mode
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#define IOART_TRGREDG 0x00000000 // edge
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#define IOART_TRGRLVL 0x00008000 // level
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#define IOART_REM_IRR 0x00004000 // RO: remote IRR
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#define IOART_INTPOL 0x00002000 // R/W: INT input pin polarity
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#define IOART_INTAHI 0x00000000 // active high
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#define IOART_INTALO 0x00002000 // active low
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#define IOART_DELIVS 0x00001000 // RO: delivery status
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#define IOART_DESTMOD 0x00000800 // R/W: destination mode
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#define IOART_DESTPHY 0x00000000 // physical
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#define IOART_DESTLOG 0x00000800 // logical
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#define IOART_DELMOD 0x00000700 // R/W: delivery mode
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#define IOART_DELFIXED 0x00000000 // fixed
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#define IOART_DELLOPRI 0x00000100 // lowest priority
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#define IOART_DELSMI 0x00000200 // System Management INT
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#define IOART_DELRSV1 0x00000300 // reserved
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#define IOART_DELNMI 0x00000400 // NMI signal
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#define IOART_DELINIT 0x00000500 // INIT signal
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#define IOART_DELRSV2 0x00000600 // reserved
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#define IOART_DELEXINT 0x00000700 // External INTerrupt
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#define IOART_INTVEC 0x000000ff // R/W: INTerrupt vector field
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// Fields in VER
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#define IOART_VER_VERSION 0x000000ff
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#define IOART_VER_MAXREDIR 0x00ff0000
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#define MAXREDIRSHIFT 16
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153
lapic.c
153
lapic.c
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@ -1,132 +1,91 @@
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// The local APIC manages internal (non-I/O) interrupts.
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// See Chapter 8 & Appendix C of Intel processor manual volume 3.
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#include "types.h"
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#include "mp.h"
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#include "defs.h"
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#include "param.h"
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#include "x86.h"
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#include "traps.h"
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#include "mmu.h"
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#include "proc.h"
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#include "lapic.h"
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// Local APIC registers, divided by 4 for use as uint[] indices.
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#define ID (0x0020/4) // ID
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#define VER (0x0030/4) // Version
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#define TPR (0x0080/4) // Task Priority
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#define APR (0x0090/4) // Arbitration Priority
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#define PPR (0x00A0/4) // Processor Priority
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#define EOI (0x00B0/4) // EOI
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#define LDR (0x00D0/4) // Logical Destination
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#define DFR (0x00E0/4) // Destination Format
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#define SVR (0x00F0/4) // Spurious Interrupt Vector
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#define ISR (0x0100/4) // Interrupt Status (8 registers)
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#define TMR (0x0180/4) // Trigger Mode (8 registers)
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#define IRR (0x0200/4) // Interrupt Request (8 registers)
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#define ENABLE 0x00000100 // Unit Enable
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#define ESR (0x0280/4) // Error Status
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#define ICRLO (0x0300/4) // Interrupt Command
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#define INIT 0x00000500 // INIT/RESET
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#define STARTUP 0x00000600 // Startup IPI
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#define DELIVS 0x00001000 // Delivery status
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#define ASSERT 0x00004000 // Assert interrupt (vs deassert)
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#define LEVEL 0x00008000 // Level triggered
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#define BCAST 0x00080000 // Send to all APICs, including self.
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#define ICRHI (0x0310/4) // Interrupt Command [63:32]
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#define TIMER (0x0320/4) // Local Vector Table 0 (TIMER)
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#define X1 0x0000000B // divide counts by 1
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#define PERIODIC 0x00020000 // Periodic
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#define PCINT (0x0340/4) // Performance Counter LVT
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#define LINT0 (0x0350/4) // Local Vector Table 1 (LINT0)
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#define LINT1 (0x0360/4) // Local Vector Table 2 (LINT1)
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#define ERROR (0x0370/4) // Local Vector Table 3 (ERROR)
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#define MASKED 0x00010000 // Interrupt masked
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#define TICR (0x0380/4) // Timer Initial Count
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#define TCCR (0x0390/4) // Timer Current Count
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#define TDCR (0x03E0/4) // Timer Divide Configuration
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// SVR
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#define ENABLE 0x00000100 // Unit Enable
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#define FOCUS 0x00000200 // Focus Processor Checking Disable
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// ICRLO
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// [14] IPI Trigger Mode Level (RW)
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#define DEASSERT 0x00000000 // Deassert level-sensitive interrupt
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#define ASSERT 0x00004000 // Assert level-sensitive interrupt
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// [17:16] Remote Read Status
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#define INVALID 0x00000000 // Invalid
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#define WAIT 0x00010000 // In-Progress
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#define VALID 0x00020000 // Valid
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// [19:18] Destination Shorthand
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#define FIELD 0x00000000 // No shorthand
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#define SELF 0x00040000 // Self is single destination
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#define ALLINC 0x00080000 // All including self
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#define ALLEXC 0x000C0000 // All Excluding self
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// ESR
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#define SENDCS 0x00000001 // Send CS Error
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#define RCVCS 0x00000002 // Receive CS Error
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#define SENDACCEPT 0x00000004 // Send Accept Error
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#define RCVACCEPT 0x00000008 // Receive Accept Error
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#define SENDVECTOR 0x00000020 // Send Illegal Vector
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#define RCVVECTOR 0x00000040 // Receive Illegal Vector
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#define REGISTER 0x00000080 // Illegal Register Address
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// [17] Timer Mode (RW)
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#define ONESHOT 0x00000000 // One-shot
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#define PERIODIC 0x00020000 // Periodic
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// [19:18] Timer Base (RW)
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#define CLKIN 0x00000000 // use CLKIN as input
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#define TMBASE 0x00040000 // use TMBASE
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#define DIVIDER 0x00080000 // use output of the divider
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#define X2 0x00000000 // divide by 2
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#define X4 0x00000001 // divide by 4
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#define X8 0x00000002 // divide by 8
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#define X16 0x00000003 // divide by 16
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#define X32 0x00000008 // divide by 32
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#define X64 0x00000009 // divide by 64
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#define X128 0x0000000A // divide by 128
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#define X1 0x0000000B // divide by 1
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//PAGEBREAK!
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volatile uint *lapic; // Initialized in mp.c
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//PAGEBREAK!
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void
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lapic_init(int c)
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{
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uint r, lvt;
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if(!lapic)
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return;
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lapic[DFR] = 0xFFFFFFFF; // Set dst format register
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r = (lapic[ID]>>24) & 0xFF; // Read APIC ID
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lapic[LDR] = (1<<r) << 24;
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lapic[TPR] = 0xFF; // No interrupts for now
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// Enable APIC
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// Enable local APIC; set spurious interrupt vector.
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lapic[SVR] = ENABLE | (IRQ_OFFSET+IRQ_SPURIOUS);
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// In virtual wire mode, set up the LINT0 and LINT1 as follows:
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lapic[LINT0] = APIC_IMASK | APIC_EXTINT;
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lapic[LINT1] = APIC_IMASK | APIC_NMI;
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// The timer repeatedly counts down at bus frequency
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// from lapic[TICR] and then issues an interrupt.
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// Lapic[TCCR] is the current counter value.
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// If xv6 cared more about precise timekeeping, the
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// values of TICR and TCCR would be calibrated using
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// an external time source.
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lapic[TDCR] = X1;
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lapic[TICR] = 10000000;
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lapic[TCCR] = 10000000;
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lapic[TIMER] = PERIODIC | (IRQ_OFFSET + IRQ_TIMER);
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lapic[EOI] = 0; // Ack any outstanding interrupts.
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// Disable logical interrupt lines.
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lapic[LINT0] = MASKED;
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lapic[LINT1] = MASKED;
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lvt = (lapic[VER]>>16) & 0xFF;
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if(lvt >= 4)
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lapic[PCINT] = APIC_IMASK;
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// Disable performance counter overflow interrupts
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// on machines that provide that interrupt entry.
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if(((lapic[VER]>>16) & 0xFF) >= 4)
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lapic[PCINT] = MASKED;
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// Map error interrupt to IRQ_ERROR.
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lapic[ERROR] = IRQ_OFFSET+IRQ_ERROR;
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lapic[ESR] = 0;
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lapic[ESR];
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// Issue an INIT Level De-Assert to synchronise arbitration ID's.
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// Clear error status register (requires back-to-back writes).
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lapic[ESR] = 0;
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lapic[ESR] = 0;
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// Ack any outstanding interrupts.
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lapic[EOI] = 0;
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// Send an Init Level De-Assert to synchronise arbitration ID's.
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lapic[ICRHI] = 0;
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lapic[ICRLO] = ALLINC | APIC_LEVEL |
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DEASSERT | APIC_INIT;
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while(lapic[ICRLO] & APIC_DELIVS)
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lapic[ICRLO] = BCAST | INIT | LEVEL;
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while(lapic[ICRLO] & DELIVS)
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;
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// Initialize the interrupt timer.
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// On real hardware would need to do more XXX.
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lapic[TDCR] = X1;
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lapic[TIMER] = CLKIN | PERIODIC | (IRQ_OFFSET + IRQ_TIMER);
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lapic[TCCR] = 10000000;
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lapic[TICR] = 10000000;
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// Enable interrupts on the APIC (but not on processor).
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// Enable interrupts on the APIC (but not on the processor).
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lapic[TPR] = 0;
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}
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|
||||
|
|
@ -146,22 +105,34 @@ lapic_eoi(void)
|
|||
lapic[EOI] = 0;
|
||||
}
|
||||
|
||||
// Spin for a given number of microseconds.
|
||||
// On real hardware would want to tune this dynamically.
|
||||
static void
|
||||
microdelay(int us)
|
||||
{
|
||||
volatile int j = 0;
|
||||
|
||||
while(us-- > 0)
|
||||
for(j=0; j<10000; j++);
|
||||
}
|
||||
|
||||
// Start additional processor running bootstrap code at addr.
|
||||
// See Appendix B of MultiProcessor Specification.
|
||||
void
|
||||
lapic_startap(uchar apicid, uint addr)
|
||||
{
|
||||
int i;
|
||||
volatile int j = 0;
|
||||
|
||||
// Send INIT interrupt to reset other CPU.
|
||||
lapic[ICRHI] = apicid<<24;
|
||||
lapic[ICRLO] = FIELD | APIC_LEVEL | ASSERT | APIC_INIT;
|
||||
for(j=0; j<10000; j++); // 200us
|
||||
lapic[ICRLO] = FIELD | APIC_LEVEL | DEASSERT | APIC_INIT;
|
||||
for(j=0; j<1000000; j++); // 10ms
|
||||
lapic[ICRLO] = INIT | LEVEL;
|
||||
microdelay(10);
|
||||
|
||||
// Send startup IPI (twice!) to enter bootstrap code.
|
||||
for(i = 0; i < 2; i++){
|
||||
lapic[ICRHI] = apicid<<24;
|
||||
lapic[ICRLO] = FIELD | APIC_EDGE | APIC_STARTUP | (addr/4096);
|
||||
lapic[ICRLO] = STARTUP | (addr>>12);
|
||||
for(j=0; j<10000; j++); // 200us
|
||||
}
|
||||
}
|
||||
|
|
|
|||
34
main.c
34
main.c
|
|
@ -12,6 +12,8 @@
|
|||
|
||||
extern char edata[], end[];
|
||||
|
||||
void bootothers(void);
|
||||
|
||||
// Bootstrap processor starts running C code here.
|
||||
// This is called main0 not main so that it can have
|
||||
// a void return type. Gcc can't handle functions named
|
||||
|
|
@ -37,7 +39,7 @@ main0(void)
|
|||
asm volatile("movl %0, %%ebp" : : "r" (cpus[bcpu].mpstack+MPSTACK));
|
||||
|
||||
lapic_init(bcpu);
|
||||
cprintf("\ncpu%d: starting xv6\n\n", cpu());
|
||||
cprintf("\\ncpu%d: starting xv6\\n\\n", cpu());
|
||||
|
||||
pinit(); // process table
|
||||
binit(); // buffer cache
|
||||
|
|
@ -51,7 +53,7 @@ main0(void)
|
|||
setupsegs(0); // segments & TSS
|
||||
console_init(); // I/O devices & their interrupts
|
||||
ide_init(); // disk
|
||||
mp_startthem(); // other CPUs
|
||||
bootothers(); // boot other CPUs
|
||||
if(!ismp)
|
||||
pit8253_timerinit(); // uniprocessor timer
|
||||
userinit(); // first user process
|
||||
|
|
@ -67,7 +69,7 @@ main0(void)
|
|||
void
|
||||
mpmain(void)
|
||||
{
|
||||
cprintf("cpu%d: starting\n", cpu());
|
||||
cprintf("cpu%d: starting\\n", cpu());
|
||||
idtinit();
|
||||
lapic_init(cpu());
|
||||
setupsegs(0);
|
||||
|
|
@ -82,3 +84,29 @@ mpmain(void)
|
|||
scheduler();
|
||||
}
|
||||
|
||||
void
|
||||
bootothers(void)
|
||||
{
|
||||
extern uchar _binary_bootother_start[], _binary_bootother_size[];
|
||||
uchar *code;
|
||||
struct cpu *c;
|
||||
|
||||
// Write bootstrap code to unused memory at 0x7000.
|
||||
code = (uchar*)0x7000;
|
||||
memmove(code, _binary_bootother_start, (uint)_binary_bootother_size);
|
||||
|
||||
for(c = cpus; c < cpus+ncpu; c++){
|
||||
if(c == cpus+cpu()) // We've started already.
|
||||
continue;
|
||||
|
||||
// Set target %esp, %eip
|
||||
*(void**)(code-4) = c->mpstack + MPSTACK;
|
||||
*(void**)(code-8) = mpmain;
|
||||
lapic_startap(c->apicid, (uint)code);
|
||||
|
||||
// Wait for cpu to get through bootstrap.
|
||||
while(c->booted == 0)
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
204
mp.c
204
mp.c
|
|
@ -1,3 +1,5 @@
|
|||
// http://developer.intel.com/design/pentium/datashts/24201606.pdf
|
||||
|
||||
#include "types.h"
|
||||
#include "mp.h"
|
||||
#include "defs.h"
|
||||
|
|
@ -7,52 +9,39 @@
|
|||
#include "mmu.h"
|
||||
#include "proc.h"
|
||||
|
||||
static char *buses[] = {
|
||||
"CBUSI ",
|
||||
"CBUSII",
|
||||
"EISA ",
|
||||
"FUTURE",
|
||||
"INTERN",
|
||||
"ISA ",
|
||||
"MBI ",
|
||||
"MBII ",
|
||||
"MCA ",
|
||||
"MPI ",
|
||||
"MPSA ",
|
||||
"NUBUS ",
|
||||
"PCI ",
|
||||
"PCMCIA",
|
||||
"TC ",
|
||||
"VL ",
|
||||
"VME ",
|
||||
"XPRESS",
|
||||
0,
|
||||
};
|
||||
|
||||
struct cpu cpus[NCPU];
|
||||
static struct cpu *bcpu;
|
||||
int ismp;
|
||||
int ncpu;
|
||||
uchar ioapic_id;
|
||||
|
||||
static struct cpu *bcpu;
|
||||
static struct mp *mp; // The floating MP structure
|
||||
|
||||
static struct mp*
|
||||
mp_scan(uchar *addr, int len)
|
||||
int
|
||||
mp_bcpu(void)
|
||||
{
|
||||
uchar *e, *p, sum;
|
||||
int i;
|
||||
return bcpu-cpus;
|
||||
}
|
||||
|
||||
static uchar
|
||||
sum(uchar *addr, int len)
|
||||
{
|
||||
int i, sum;
|
||||
|
||||
sum = 0;
|
||||
for(i=0; i<len; i++)
|
||||
sum += addr[i];
|
||||
return sum;
|
||||
}
|
||||
|
||||
// Look for an MP structure in the len bytes at addr.
|
||||
static struct mp*
|
||||
mp_search1(uchar *addr, int len)
|
||||
{
|
||||
uchar *e, *p;
|
||||
|
||||
e = addr+len;
|
||||
for(p = addr; p < e; p += sizeof(struct mp)){
|
||||
if(memcmp(p, "_MP_", 4))
|
||||
continue;
|
||||
sum = 0;
|
||||
for(i = 0; i < sizeof(struct mp); i++)
|
||||
sum += p[i];
|
||||
if(sum == 0)
|
||||
for(p = addr; p < e; p += sizeof(struct mp))
|
||||
if(memcmp(p, "_MP_", 4) == 0 && sum(p, sizeof(struct mp)) == 0)
|
||||
return (struct mp*)p;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -68,16 +57,16 @@ mp_search(void)
|
|||
uint p;
|
||||
struct mp *mp;
|
||||
|
||||
bda = (uchar*) 0x400;
|
||||
bda = (uchar*)0x400;
|
||||
if((p = (bda[0x0F]<<8)|bda[0x0E])){
|
||||
if((mp = mp_scan((uchar*) p, 1024)))
|
||||
if((mp = mp_search1((uchar*)p, 1024)))
|
||||
return mp;
|
||||
}else{
|
||||
p = ((bda[0x14]<<8)|bda[0x13])*1024;
|
||||
if((mp = mp_scan((uchar*)p-1024, 1024)))
|
||||
if((mp = mp_search1((uchar*)p-1024, 1024)))
|
||||
return mp;
|
||||
}
|
||||
return mp_scan((uchar*)0xF0000, 0x10000);
|
||||
return mp_search1((uchar*)0xF0000, 0x10000);
|
||||
}
|
||||
|
||||
// Search for an MP configuration table. For now,
|
||||
|
|
@ -85,93 +74,64 @@ mp_search(void)
|
|||
// Check for correct signature, calculate the checksum and,
|
||||
// if correct, check the version.
|
||||
// To do: check extended table checksum.
|
||||
static int
|
||||
mp_detect(void)
|
||||
static struct mpconf*
|
||||
mp_config(struct mp **pmp)
|
||||
{
|
||||
struct mpctb *pcmp;
|
||||
uchar *p, sum;
|
||||
uint length;
|
||||
struct mpconf *conf;
|
||||
struct mp *mp;
|
||||
|
||||
if((mp = mp_search()) == 0 || mp->physaddr == 0)
|
||||
return -1;
|
||||
|
||||
pcmp = (struct mpctb*) mp->physaddr;
|
||||
if(memcmp(pcmp, "PCMP", 4) != 0)
|
||||
return -1;
|
||||
if(pcmp->version != 1 && pcmp->version != 4)
|
||||
return -1;
|
||||
|
||||
length = pcmp->length;
|
||||
sum = 0;
|
||||
for(p = (uchar*)pcmp; length; length--)
|
||||
sum += *p++;
|
||||
if(sum != 0)
|
||||
return -1;
|
||||
|
||||
return 0;
|
||||
conf = (struct mpconf*)mp->physaddr;
|
||||
if(memcmp(conf, "PCMP", 4) != 0)
|
||||
return 0;
|
||||
if(conf->version != 1 && conf->version != 4)
|
||||
return 0;
|
||||
if(sum((uchar*)conf, conf->length) != 0)
|
||||
return 0;
|
||||
*pmp = mp;
|
||||
return conf;
|
||||
}
|
||||
|
||||
void
|
||||
mp_init(void)
|
||||
{
|
||||
int i;
|
||||
uchar *p, *e;
|
||||
struct mpctb *mpctb;
|
||||
struct mppe *proc;
|
||||
struct mpbe *bus;
|
||||
struct mp *mp;
|
||||
struct mpconf *conf;
|
||||
struct mpproc *proc;
|
||||
struct mpioapic *ioapic;
|
||||
struct mpie *intr;
|
||||
|
||||
ncpu = 0;
|
||||
if(mp_detect() < 0)
|
||||
bcpu = &cpus[ncpu];
|
||||
if((conf = mp_config(&mp)) == 0)
|
||||
return;
|
||||
|
||||
ismp = 1;
|
||||
lapic = (uint*)conf->lapicaddr;
|
||||
|
||||
// Run through the table saving information needed for starting
|
||||
// application processors and initialising any I/O APICs. The table
|
||||
// is guaranteed to be in order such that only one pass is necessary.
|
||||
|
||||
mpctb = (struct mpctb*)mp->physaddr;
|
||||
lapic = (uint*)mpctb->lapicaddr;
|
||||
p = (uchar*)mpctb + sizeof(*mpctb);
|
||||
e = (uchar*)mpctb + mpctb->length;
|
||||
|
||||
while(p < e) {
|
||||
for(p=(uchar*)(conf+1), e=(uchar*)conf+conf->length; p<e; ){
|
||||
switch(*p){
|
||||
case MPPROCESSOR:
|
||||
proc = (struct mppe*) p;
|
||||
case MPPROC:
|
||||
proc = (struct mpproc*)p;
|
||||
cpus[ncpu].apicid = proc->apicid;
|
||||
if(proc->flags & MPBP) {
|
||||
if(proc->flags & MPBOOT)
|
||||
bcpu = &cpus[ncpu];
|
||||
}
|
||||
ncpu++;
|
||||
p += sizeof(struct mppe);
|
||||
continue;
|
||||
case MPBUS:
|
||||
bus = (struct mpbe*) p;
|
||||
for(i = 0; buses[i]; i++){
|
||||
if(strncmp(buses[i], bus->string, sizeof(bus->string)) == 0)
|
||||
break;
|
||||
}
|
||||
p += sizeof(struct mpbe);
|
||||
p += sizeof(struct mpproc);
|
||||
continue;
|
||||
case MPIOAPIC:
|
||||
ioapic = (struct mpioapic*) p;
|
||||
ioapic = (struct mpioapic*)p;
|
||||
ioapic_id = ioapic->apicno;
|
||||
p += sizeof(struct mpioapic);
|
||||
continue;
|
||||
case MPBUS:
|
||||
case MPIOINTR:
|
||||
intr = (struct mpie*) p;
|
||||
p += sizeof(struct mpie);
|
||||
case MPLINTR:
|
||||
p += 8;
|
||||
continue;
|
||||
default:
|
||||
cprintf("mp_init: unknown PCMP type 0x%x (e-p 0x%x)\n", *p, e-p);
|
||||
while(p < e){
|
||||
cprintf("%uX ", *p);
|
||||
p++;
|
||||
}
|
||||
break;
|
||||
cprintf("mp_init: unknown config type %x\n", *p);
|
||||
panic("mp_init");
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -182,47 +142,3 @@ mp_init(void)
|
|||
outb(0x23, inb(0x23) | 1); // Mask external interrupts.
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
int
|
||||
mp_bcpu(void)
|
||||
{
|
||||
if(ismp)
|
||||
return bcpu-cpus;
|
||||
return 0;
|
||||
}
|
||||
|
||||
extern void mpmain(void);
|
||||
|
||||
// Write bootstrap code to unused memory at 0x7000.
|
||||
#define APBOOTCODE 0x7000
|
||||
|
||||
void
|
||||
mp_startthem(void)
|
||||
{
|
||||
extern uchar _binary_bootother_start[], _binary_bootother_size[];
|
||||
extern int main();
|
||||
int c;
|
||||
|
||||
memmove((void*) APBOOTCODE,_binary_bootother_start,
|
||||
(uint) _binary_bootother_size);
|
||||
|
||||
for(c = 0; c < ncpu; c++){
|
||||
// Our current cpu has already started.
|
||||
if(c == cpu())
|
||||
continue;
|
||||
|
||||
// Set target %esp
|
||||
*(uint*)(APBOOTCODE-4) = (uint) (cpus[c].mpstack) + MPSTACK;
|
||||
|
||||
// Set target %eip
|
||||
*(uint*)(APBOOTCODE-8) = (uint)mpmain;
|
||||
|
||||
// Go!
|
||||
lapic_startap(cpus[c].apicid, (uint)APBOOTCODE);
|
||||
|
||||
// Wait for cpu to get through bootstrap.
|
||||
while(cpus[c].booted == 0)
|
||||
;
|
||||
}
|
||||
}
|
||||
|
|
|
|||
84
mp.h
84
mp.h
|
|
@ -1,4 +1,4 @@
|
|||
// See MultiProcessor Specification Version 1.[14].
|
||||
// See MultiProcessor Specification Version 1.[14]
|
||||
|
||||
struct mp { // floating pointer
|
||||
uchar signature[4]; // "_MP_"
|
||||
|
|
@ -11,7 +11,7 @@ struct mp { // floating pointer
|
|||
uchar reserved[3];
|
||||
};
|
||||
|
||||
struct mpctb { // configuration table header
|
||||
struct mpconf { // configuration table header
|
||||
uchar signature[4]; // "PCMP"
|
||||
ushort length; // total table length
|
||||
uchar version; // [14]
|
||||
|
|
@ -26,22 +26,17 @@ struct mpctb { // configuration table header
|
|||
uchar reserved;
|
||||
};
|
||||
|
||||
struct mppe { // processor table entry
|
||||
struct mpproc { // processor table entry
|
||||
uchar type; // entry type (0)
|
||||
uchar apicid; // local APIC id
|
||||
uchar version; // local APIC verison
|
||||
uchar flags; // CPU flags
|
||||
#define MPBOOT 0x02 // This proc is the bootstrap processor.
|
||||
uchar signature[4]; // CPU signature
|
||||
uint feature; // feature flags from CPUID instruction
|
||||
uchar reserved[8];
|
||||
};
|
||||
|
||||
struct mpbe { // bus table entry
|
||||
uchar type; // entry type (1)
|
||||
uchar busno; // bus id
|
||||
char string[6]; // bus type string
|
||||
};
|
||||
|
||||
struct mpioapic { // I/O APIC table entry
|
||||
uchar type; // entry type (2)
|
||||
uchar apicno; // I/O APIC id
|
||||
|
|
@ -50,69 +45,10 @@ struct mpioapic { // I/O APIC table entry
|
|||
uint *addr; // I/O APIC address
|
||||
};
|
||||
|
||||
struct mpie { // interrupt table entry
|
||||
uchar type; // entry type ([34])
|
||||
uchar intr; // interrupt type
|
||||
ushort flags; // interrupt flag
|
||||
uchar busno; // source bus id
|
||||
uchar irq; // source bus irq
|
||||
uchar apicno; // destination APIC id
|
||||
uchar intin; // destination APIC [L]INTIN#
|
||||
};
|
||||
// Table entry types
|
||||
#define MPPROC 0x00 // One per processor
|
||||
#define MPBUS 0x01 // One per bus
|
||||
#define MPIOAPIC 0x02 // One per I/O APIC
|
||||
#define MPIOINTR 0x03 // One per bus interrupt source
|
||||
#define MPLINTR 0x04 // One per system interrupt source
|
||||
|
||||
enum { // table entry types
|
||||
MPPROCESSOR = 0x00, // one entry per processor
|
||||
MPBUS = 0x01, // one entry per bus
|
||||
MPIOAPIC = 0x02, // one entry per I/O APIC
|
||||
MPIOINTR = 0x03, // one entry per bus interrupt source
|
||||
MPLINTR = 0x04, // one entry per system interrupt source
|
||||
|
||||
MPSASM = 0x80,
|
||||
MPHIERARCHY = 0x81,
|
||||
MPCBASM = 0x82,
|
||||
|
||||
// PCMPprocessor and PCMPioapic flags
|
||||
MPEN = 0x01, // enabled
|
||||
MPBP = 0x02, // bootstrap processor
|
||||
|
||||
// PCMPiointr and PCMPlintr flags
|
||||
MPPOMASK = 0x03, // polarity conforms to bus specs
|
||||
MPHIGH = 0x01, // active high
|
||||
MPLOW = 0x03, // active low
|
||||
MPELMASK = 0x0C, // trigger mode of APIC input signals
|
||||
MPEDGE = 0x04, // edge-triggered
|
||||
MPLEVEL = 0x0C, // level-triggered
|
||||
|
||||
// PCMPiointr and PCMPlintr interrupt type
|
||||
MPINT = 0x00, // vectored interrupt from APIC Rdt
|
||||
MPNMI = 0x01, // non-maskable interrupt
|
||||
MPSMI = 0x02, // system management interrupt
|
||||
MPExtINT = 0x03, // vectored interrupt from external PIC
|
||||
};
|
||||
|
||||
// Common bits for
|
||||
// I/O APIC Redirection Table Entry;
|
||||
// Local APIC Local Interrupt Vector Table;
|
||||
// Local APIC Inter-Processor Interrupt;
|
||||
// Local APIC Timer Vector Table.
|
||||
enum {
|
||||
APIC_FIXED = 0x00000000, // [10:8] Delivery Mode
|
||||
APIC_LOWEST = 0x00000100, // Lowest priority
|
||||
APIC_SMI = 0x00000200, // System Management Interrupt
|
||||
APIC_RR = 0x00000300, // Remote Read
|
||||
APIC_NMI = 0x00000400,
|
||||
APIC_INIT = 0x00000500, // INIT/RESET
|
||||
APIC_STARTUP = 0x00000600, // Startup IPI
|
||||
APIC_EXTINT = 0x00000700,
|
||||
|
||||
APIC_PHYSICAL = 0x00000000, // [11] Destination Mode (RW)
|
||||
APIC_LOGICAL = 0x00000800,
|
||||
|
||||
APIC_DELIVS = 0x00001000, // [12] Delivery Status (RO)
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APIC_HIGH = 0x00000000, // [13] Interrupt Input Pin Polarity (RW)
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APIC_LOW = 0x00002000,
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APIC_REMOTEIRR = 0x00004000, // [14] Remote IRR (RO)
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APIC_EDGE = 0x00000000, // [15] Trigger Mode (RW)
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APIC_LEVEL = 0x00008000,
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APIC_IMASK = 0x00010000, // [16] Interrupt Mask
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};
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||||
|
|
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Loading…
Reference in a new issue