add some comments
find out the hard way why user and kernel must have separate segment descriptors
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c99599784e
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1afc9d3fca
6 changed files with 30 additions and 19 deletions
2
asm.h
2
asm.h
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@ -6,6 +6,8 @@
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.word 0, 0; \
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.word 0, 0; \
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.byte 0, 0, 0, 0
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.byte 0, 0, 0, 0
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// The 0xC0 means the limit is in 4096-byte units
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// and (for executable segments) 32-bit mode.
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#define SEG_ASM(type,base,lim) \
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#define SEG_ASM(type,base,lim) \
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.word (((lim) >> 12) & 0xffff), ((base) & 0xffff); \
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.word (((lim) >> 12) & 0xffff), ((base) & 0xffff); \
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.byte (((base) >> 16) & 0xff), (0x90 | (type)), \
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.byte (((base) >> 16) & 0xff), (0x90 | (type)), \
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@ -51,8 +51,10 @@ seta20.2:
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orl $CR0_PE, %eax
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orl $CR0_PE, %eax
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movl %eax, %cr0
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movl %eax, %cr0
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# Jump to next instruction, but in 32-bit code segment.
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# This ljmp is how you load the CS (Code Segment) register.
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# Switches processor into 32-bit mode.
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# SEG_ASM produces segment descriptors with the 32-bit mode
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# flag set (the D flag), so addresses and word operands will
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# default to 32 bits after this jump.
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ljmp $(SEG_KCODE<<3), $start32
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ljmp $(SEG_KCODE<<3), $start32
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.code32 # Assemble for 32-bit mode
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.code32 # Assemble for 32-bit mode
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@ -45,8 +45,10 @@ start:
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orl $CR0_PE, %eax
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orl $CR0_PE, %eax
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movl %eax, %cr0
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movl %eax, %cr0
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# Jump to next instruction, but in 32-bit code segment.
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# This ljmp is how you load the CS (Code Segment) register.
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# Switches processor into 32-bit mode.
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# SEG_ASM produces segment descriptors with the 32-bit mode
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# flag set (the D flag), so addresses and word operands will
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# default to 32 bits after this jump.
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ljmp $(SEG_KCODE<<3), $start32
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ljmp $(SEG_KCODE<<3), $start32
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.code32 # Assemble for 32-bit mode
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.code32 # Assemble for 32-bit mode
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22
main.c
22
main.c
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@ -16,13 +16,13 @@ main(void)
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{
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{
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mpinit(); // collect info about this machine
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mpinit(); // collect info about this machine
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lapicinit(mpbcpu());
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lapicinit(mpbcpu());
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ksegment();
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ksegment(); // set up segments
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picinit(); // interrupt controller
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picinit(); // interrupt controller
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ioapicinit(); // another interrupt controller
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ioapicinit(); // another interrupt controller
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consoleinit(); // I/O devices & their interrupts
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consoleinit(); // I/O devices & their interrupts
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uartinit(); // serial port
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uartinit(); // serial port
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pminit(); // physical memory for kernel
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pminit(); // discover how much memory there is
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jkstack(); // Jump to mainc on a properly-allocated stack
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jkstack(); // call mainc() on a properly-allocated stack
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}
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}
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void
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void
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@ -41,7 +41,7 @@ void
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mainc(void)
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mainc(void)
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{
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{
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cprintf("\ncpu%d: starting xv6\n\n", cpu->id);
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cprintf("\ncpu%d: starting xv6\n\n", cpu->id);
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kvmalloc(); // allocate the kernel page table
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kvmalloc(); // initialze the kernel page table
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pinit(); // process table
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pinit(); // process table
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tvinit(); // trap vectors
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tvinit(); // trap vectors
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binit(); // buffer cache
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binit(); // buffer cache
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@ -57,8 +57,9 @@ mainc(void)
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mpmain();
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mpmain();
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}
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}
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// Bootstrap processor gets here after setting up the hardware.
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// Common CPU setup code.
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// Additional processors start here.
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// Bootstrap CPU comes here from mainc().
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// Other CPUs jump here from bootother.S.
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static void
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static void
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mpmain(void)
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mpmain(void)
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{
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{
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@ -66,11 +67,11 @@ mpmain(void)
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ksegment();
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ksegment();
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lapicinit(cpunum());
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lapicinit(cpunum());
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}
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}
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vminit(); // Run with paging on each processor
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vminit(); // turn on paging
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cprintf("cpu%d: starting\n", cpu->id);
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cprintf("cpu%d: starting\n", cpu->id);
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idtinit();
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idtinit(); // load idt register
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xchg(&cpu->booted, 1);
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xchg(&cpu->booted, 1);
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scheduler();
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scheduler(); // start running processes
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}
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}
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static void
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static void
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@ -85,6 +86,7 @@ bootothers(void)
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// placed the start of bootother.S there.
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// placed the start of bootother.S there.
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code = (uchar *) 0x7000;
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code = (uchar *) 0x7000;
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memmove(code, _binary_bootother_start, (uint)_binary_bootother_size);
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memmove(code, _binary_bootother_start, (uint)_binary_bootother_size);
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for(c = cpus; c < cpus+ncpu; c++){
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for(c = cpus; c < cpus+ncpu; c++){
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if(c == cpus+cpunum()) // We've started already.
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if(c == cpus+cpunum()) // We've started already.
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continue;
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continue;
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@ -95,7 +97,7 @@ bootothers(void)
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*(void**)(code-8) = mpmain;
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*(void**)(code-8) = mpmain;
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lapicstartap(c->id, (uint)code);
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lapicstartap(c->id, (uint)code);
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// Wait for cpu to get through bootstrap.
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// Wait for cpu to finish mpmain()
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while(c->booted == 0)
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while(c->booted == 0)
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;
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;
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}
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}
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4
proc.h
4
proc.h
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@ -3,8 +3,8 @@
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#define SEG_KCODE 1 // kernel code
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#define SEG_KCODE 1 // kernel code
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#define SEG_KDATA 2 // kernel data+stack
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#define SEG_KDATA 2 // kernel data+stack
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#define SEG_KCPU 3 // kernel per-cpu data
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#define SEG_KCPU 3 // kernel per-cpu data
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#define SEG_UCODE 4
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#define SEG_UCODE 4 // user code
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#define SEG_UDATA 5
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#define SEG_UDATA 5 // user data+stack
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#define SEG_TSS 6 // this process's task state
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#define SEG_TSS 6 // this process's task state
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#define NSEGS 7
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#define NSEGS 7
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9
vm.c
9
vm.c
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@ -93,12 +93,15 @@ ksegment(void)
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{
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{
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struct cpu *c;
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struct cpu *c;
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// Map once virtual addresses to linear addresses using identity map
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// Map virtual addresses to linear addresses using identity map.
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// Cannot share a CODE descriptor for both kernel and user
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// because it would have to have DPL_USR, but the CPU forbids
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// an interrupt from CPL=0 to DPL=3.
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c = &cpus[cpunum()];
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c = &cpus[cpunum()];
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c->gdt[SEG_KCODE] = SEG(STA_X|STA_R, 0, 0xffffffff, 0);
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c->gdt[SEG_KCODE] = SEG(STA_X|STA_R, 0, 0xffffffff, 0);
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c->gdt[SEG_KDATA] = SEG(STA_W, 0, 0xffffffff, 0);
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c->gdt[SEG_KDATA] = SEG(STA_W, 0, 0xffffffff, 0);
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c->gdt[SEG_UCODE] = SEG(STA_X|STA_R, 0x0, 0xffffffff, DPL_USER);
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c->gdt[SEG_UCODE] = SEG(STA_X|STA_R, 0, 0xffffffff, DPL_USER);
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c->gdt[SEG_UDATA] = SEG(STA_W, 0x0, 0xffffffff, DPL_USER);
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c->gdt[SEG_UDATA] = SEG(STA_W, 0, 0xffffffff, DPL_USER);
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// map cpu, and curproc
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// map cpu, and curproc
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c->gdt[SEG_KCPU] = SEG(STA_W, &c->cpu, 8, 0);
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c->gdt[SEG_KCPU] = SEG(STA_W, &c->cpu, 8, 0);
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