49 lines
1.6 KiB
C
49 lines
1.6 KiB
C
// RUN: %clang -target mipsel-unknown-linux -S -o - -emit-llvm %s \
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// RUN: | FileCheck %s
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// This checks that the frontend will accept inline asm constraints
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// c', 'l' and 'x'.
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int main()
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{
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// 'c': 16 bit address register for Mips16, GPR for all others
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// I am using 'c' to constrain both the target and one of the source
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// registers. We are looking for syntactical correctness.
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// CHECK: %{{[0-9]+}} = call i32 asm sideeffect "addi $0,$1,$2 \0A\09\09", "=c,c,I"(i32 %{{[0-9]+}}, i32 %{{[0-9]+}}) [[NUW:#[0-9]+]], !srcloc !{{[0-9]+}}
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int __s, __v = 17;
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int __t;
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__asm__ __volatile__(
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"addi %0,%1,%2 \n\t\t"
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: "=c" (__t)
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: "c" (__s), "I" (__v));
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// 'l': lo register
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// We are making it clear that destination register is lo with the
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// use of the 'l' constraint ("=l").
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// CHECK: %{{[0-9]+}} = call i32 asm sideeffect "mtlo $1 \0A\09\09", "=l,r,~{lo}"(i32 %{{[0-9]+}}) [[NUW]], !srcloc !{{[0-9]+}}
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int i_temp = 44;
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int i_result;
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__asm__ __volatile__(
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"mtlo %1 \n\t\t"
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: "=l" (i_result)
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: "r" (i_temp)
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: "lo");
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// 'x': Combined lo/hi registers
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// We are specifying that destination registers are the hi/lo pair with the
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// use of the 'x' constraint ("=x").
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// CHECK: %{{[0-9]+}} = call i64 asm sideeffect "mthi $1 \0A\09\09mtlo $2 \0A\09\09", "=x,r,r"(i32 %{{[0-9]+}}, i32 %{{[0-9]+}}) [[NUW]], !srcloc !{{[0-9]+}}
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int i_hi = 3;
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int i_lo = 2;
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long long ll_result = 0;
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__asm__ __volatile__(
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"mthi %1 \n\t\t"
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"mtlo %2 \n\t\t"
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: "=x" (ll_result)
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: "r" (i_hi), "r" (i_lo)
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: );
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return 0;
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}
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// CHECK: attributes [[NUW]] = { nounwind }
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