f14fb60209
* Updating common/lib * Updating lib/csu * Updating lib/libc * Updating libexec/ld.elf_so * Corrected test on __minix in featuretest to actually follow the meaning of the comment. * Cleaned up _REENTRANT-related defintions. * Disabled -D_REENTRANT for libfetch * Removing some unneeded __NBSD_LIBC defines and tests Change-Id: Ic1394baef74d11b9f86b312f5ff4bbc3cbf72ce2
375 lines
8 KiB
ArmAsm
375 lines
8 KiB
ArmAsm
/* $NetBSD: divsi3.S,v 1.3 2012/10/10 02:16:54 christos Exp $ */
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/*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <machine/asm.h>
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/*
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* stack is aligned as there's a possibility of branching to .L_overflow
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* which makes a C call
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*/
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.L_overflow:
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#if !defined(_KERNEL) && !defined(_STANDALONE)
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mov r0, #8 /* SIGFPE */
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bl PIC_SYM(_C_LABEL(raise), PLT) /* raise it */
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mov r0, #0
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#else
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/* XXX should cause a fatal error */
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mvn r0, #0
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#endif
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RET
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ENTRY_NP(__aeabi_uidivmod)
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ENTRY_NP(__aeabi_uidiv)
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ENTRY(__udivsi3)
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.L_udivide: /* r0 = r0 / r1; r1 = r0 % r1 */
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eor r0, r1, r0
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eor r1, r0, r1
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eor r0, r1, r0
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/* r0 = r1 / r0; r1 = r1 % r0 */
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cmp r0, #1
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bcc .L_overflow
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beq .L_divide_l0
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mov ip, #0
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movs r1, r1
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bpl .L_divide_l1
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orr ip, ip, #0x20000000 /* ip bit 0x20000000 = -ve r1 */
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movs r1, r1, lsr #1
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orrcs ip, ip, #0x10000000 /* ip bit 0x10000000 = bit 0 of r1 */
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b .L_divide_l1
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.L_divide_l0: /* r0 == 1 */
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mov r0, r1
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mov r1, #0
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RET
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ENTRY_NP(__aeabi_idivmod)
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ENTRY_NP(__aeabi_idiv)
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ENTRY(__divsi3)
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.L_divide: /* r0 = r0 / r1; r1 = r0 % r1 */
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eor r0, r1, r0
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eor r1, r0, r1
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eor r0, r1, r0
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/* r0 = r1 / r0; r1 = r1 % r0 */
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cmp r0, #1
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bcc .L_overflow
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beq .L_divide_l0
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ands ip, r0, #0x80000000
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rsbmi r0, r0, #0
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ands r2, r1, #0x80000000
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eor ip, ip, r2
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rsbmi r1, r1, #0
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orr ip, r2, ip, lsr #1 /* ip bit 0x40000000 = -ve division */
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/* ip bit 0x80000000 = -ve remainder */
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.L_divide_l1:
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mov r2, #1
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mov r3, #0
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/*
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* If the highest bit of the dividend is set, we have to be
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* careful when shifting the divisor. Test this.
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*/
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movs r1,r1
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bpl .L_old_code
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/*
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* At this point, the highest bit of r1 is known to be set.
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* We abuse this below in the tst instructions.
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*/
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tst r1, r0 /*, lsl #0 */
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bmi .L_divide_b1
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tst r1, r0, lsl #1
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bmi .L_divide_b2
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tst r1, r0, lsl #2
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bmi .L_divide_b3
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tst r1, r0, lsl #3
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bmi .L_divide_b4
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tst r1, r0, lsl #4
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bmi .L_divide_b5
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tst r1, r0, lsl #5
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bmi .L_divide_b6
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tst r1, r0, lsl #6
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bmi .L_divide_b7
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tst r1, r0, lsl #7
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bmi .L_divide_b8
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tst r1, r0, lsl #8
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bmi .L_divide_b9
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tst r1, r0, lsl #9
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bmi .L_divide_b10
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tst r1, r0, lsl #10
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bmi .L_divide_b11
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tst r1, r0, lsl #11
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bmi .L_divide_b12
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tst r1, r0, lsl #12
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bmi .L_divide_b13
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tst r1, r0, lsl #13
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bmi .L_divide_b14
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tst r1, r0, lsl #14
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bmi .L_divide_b15
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tst r1, r0, lsl #15
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bmi .L_divide_b16
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tst r1, r0, lsl #16
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bmi .L_divide_b17
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tst r1, r0, lsl #17
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bmi .L_divide_b18
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tst r1, r0, lsl #18
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bmi .L_divide_b19
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tst r1, r0, lsl #19
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bmi .L_divide_b20
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tst r1, r0, lsl #20
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bmi .L_divide_b21
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tst r1, r0, lsl #21
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bmi .L_divide_b22
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tst r1, r0, lsl #22
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bmi .L_divide_b23
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tst r1, r0, lsl #23
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bmi .L_divide_b24
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tst r1, r0, lsl #24
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bmi .L_divide_b25
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tst r1, r0, lsl #25
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bmi .L_divide_b26
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tst r1, r0, lsl #26
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bmi .L_divide_b27
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tst r1, r0, lsl #27
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bmi .L_divide_b28
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tst r1, r0, lsl #28
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bmi .L_divide_b29
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tst r1, r0, lsl #29
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bmi .L_divide_b30
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tst r1, r0, lsl #30
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bmi .L_divide_b31
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/*
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* instead of:
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* tst r1, r0, lsl #31
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* bmi .L_divide_b32
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*/
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b .L_divide_b32
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.L_old_code:
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cmp r1, r0
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bcc .L_divide_b0
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cmp r1, r0, lsl #1
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bcc .L_divide_b1
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cmp r1, r0, lsl #2
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bcc .L_divide_b2
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cmp r1, r0, lsl #3
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bcc .L_divide_b3
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cmp r1, r0, lsl #4
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bcc .L_divide_b4
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cmp r1, r0, lsl #5
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bcc .L_divide_b5
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cmp r1, r0, lsl #6
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bcc .L_divide_b6
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cmp r1, r0, lsl #7
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bcc .L_divide_b7
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cmp r1, r0, lsl #8
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bcc .L_divide_b8
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cmp r1, r0, lsl #9
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bcc .L_divide_b9
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cmp r1, r0, lsl #10
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bcc .L_divide_b10
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cmp r1, r0, lsl #11
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bcc .L_divide_b11
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cmp r1, r0, lsl #12
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bcc .L_divide_b12
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cmp r1, r0, lsl #13
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bcc .L_divide_b13
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cmp r1, r0, lsl #14
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bcc .L_divide_b14
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cmp r1, r0, lsl #15
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bcc .L_divide_b15
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cmp r1, r0, lsl #16
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bcc .L_divide_b16
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cmp r1, r0, lsl #17
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bcc .L_divide_b17
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cmp r1, r0, lsl #18
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bcc .L_divide_b18
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cmp r1, r0, lsl #19
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bcc .L_divide_b19
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cmp r1, r0, lsl #20
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bcc .L_divide_b20
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cmp r1, r0, lsl #21
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bcc .L_divide_b21
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cmp r1, r0, lsl #22
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bcc .L_divide_b22
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cmp r1, r0, lsl #23
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bcc .L_divide_b23
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cmp r1, r0, lsl #24
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bcc .L_divide_b24
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cmp r1, r0, lsl #25
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bcc .L_divide_b25
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cmp r1, r0, lsl #26
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bcc .L_divide_b26
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cmp r1, r0, lsl #27
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bcc .L_divide_b27
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cmp r1, r0, lsl #28
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bcc .L_divide_b28
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cmp r1, r0, lsl #29
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bcc .L_divide_b29
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cmp r1, r0, lsl #30
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bcc .L_divide_b30
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.L_divide_b32:
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cmp r1, r0, lsl #31
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subhs r1, r1,r0, lsl #31
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addhs r3, r3,r2, lsl #31
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.L_divide_b31:
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cmp r1, r0, lsl #30
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subhs r1, r1,r0, lsl #30
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addhs r3, r3,r2, lsl #30
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.L_divide_b30:
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cmp r1, r0, lsl #29
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subhs r1, r1,r0, lsl #29
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addhs r3, r3,r2, lsl #29
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.L_divide_b29:
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cmp r1, r0, lsl #28
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subhs r1, r1,r0, lsl #28
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addhs r3, r3,r2, lsl #28
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.L_divide_b28:
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cmp r1, r0, lsl #27
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subhs r1, r1,r0, lsl #27
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addhs r3, r3,r2, lsl #27
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.L_divide_b27:
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cmp r1, r0, lsl #26
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subhs r1, r1,r0, lsl #26
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addhs r3, r3,r2, lsl #26
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.L_divide_b26:
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cmp r1, r0, lsl #25
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subhs r1, r1,r0, lsl #25
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addhs r3, r3,r2, lsl #25
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.L_divide_b25:
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cmp r1, r0, lsl #24
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subhs r1, r1,r0, lsl #24
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addhs r3, r3,r2, lsl #24
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.L_divide_b24:
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cmp r1, r0, lsl #23
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subhs r1, r1,r0, lsl #23
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addhs r3, r3,r2, lsl #23
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.L_divide_b23:
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cmp r1, r0, lsl #22
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subhs r1, r1,r0, lsl #22
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addhs r3, r3,r2, lsl #22
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.L_divide_b22:
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cmp r1, r0, lsl #21
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subhs r1, r1,r0, lsl #21
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addhs r3, r3,r2, lsl #21
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.L_divide_b21:
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cmp r1, r0, lsl #20
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subhs r1, r1,r0, lsl #20
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addhs r3, r3,r2, lsl #20
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.L_divide_b20:
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cmp r1, r0, lsl #19
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subhs r1, r1,r0, lsl #19
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addhs r3, r3,r2, lsl #19
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.L_divide_b19:
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cmp r1, r0, lsl #18
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subhs r1, r1,r0, lsl #18
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addhs r3, r3,r2, lsl #18
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.L_divide_b18:
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cmp r1, r0, lsl #17
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subhs r1, r1,r0, lsl #17
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addhs r3, r3,r2, lsl #17
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.L_divide_b17:
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cmp r1, r0, lsl #16
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subhs r1, r1,r0, lsl #16
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addhs r3, r3,r2, lsl #16
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.L_divide_b16:
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cmp r1, r0, lsl #15
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subhs r1, r1,r0, lsl #15
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addhs r3, r3,r2, lsl #15
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.L_divide_b15:
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cmp r1, r0, lsl #14
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subhs r1, r1,r0, lsl #14
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addhs r3, r3,r2, lsl #14
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.L_divide_b14:
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cmp r1, r0, lsl #13
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subhs r1, r1,r0, lsl #13
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addhs r3, r3,r2, lsl #13
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.L_divide_b13:
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cmp r1, r0, lsl #12
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subhs r1, r1,r0, lsl #12
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addhs r3, r3,r2, lsl #12
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.L_divide_b12:
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cmp r1, r0, lsl #11
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subhs r1, r1,r0, lsl #11
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addhs r3, r3,r2, lsl #11
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.L_divide_b11:
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cmp r1, r0, lsl #10
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subhs r1, r1,r0, lsl #10
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addhs r3, r3,r2, lsl #10
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.L_divide_b10:
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cmp r1, r0, lsl #9
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subhs r1, r1,r0, lsl #9
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addhs r3, r3,r2, lsl #9
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.L_divide_b9:
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cmp r1, r0, lsl #8
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subhs r1, r1,r0, lsl #8
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addhs r3, r3,r2, lsl #8
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.L_divide_b8:
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cmp r1, r0, lsl #7
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subhs r1, r1,r0, lsl #7
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addhs r3, r3,r2, lsl #7
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.L_divide_b7:
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cmp r1, r0, lsl #6
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subhs r1, r1,r0, lsl #6
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addhs r3, r3,r2, lsl #6
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.L_divide_b6:
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cmp r1, r0, lsl #5
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subhs r1, r1,r0, lsl #5
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addhs r3, r3,r2, lsl #5
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.L_divide_b5:
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cmp r1, r0, lsl #4
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subhs r1, r1,r0, lsl #4
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addhs r3, r3,r2, lsl #4
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.L_divide_b4:
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cmp r1, r0, lsl #3
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subhs r1, r1,r0, lsl #3
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addhs r3, r3,r2, lsl #3
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.L_divide_b3:
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cmp r1, r0, lsl #2
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subhs r1, r1,r0, lsl #2
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addhs r3, r3,r2, lsl #2
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.L_divide_b2:
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cmp r1, r0, lsl #1
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subhs r1, r1,r0, lsl #1
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addhs r3, r3,r2, lsl #1
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.L_divide_b1:
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cmp r1, r0
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subhs r1, r1, r0
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addhs r3, r3, r2
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.L_divide_b0:
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tst ip, #0x20000000
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bne .L_udivide_l1
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mov r0, r3
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cmp ip, #0
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rsbmi r1, r1, #0
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movs ip, ip, lsl #1
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bicmi r0, r0, #0x80000000 /* Fix incase we divided 0x80000000 */
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rsbmi r0, r0, #0
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RET
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.L_udivide_l1:
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tst ip, #0x10000000
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mov r1, r1, lsl #1
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orrne r1, r1, #1
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mov r3, r3, lsl #1
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cmp r1, r0
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subhs r1, r1, r0
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addhs r3, r3, r2
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mov r0, r3
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RET
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