0ac9b6d4cf
- any cpu can use smp_schedule() to tell another cpu to reschedule - if an AP is idle, it turns off timer as there is nothing to preempt, no need to wakeup just to go back to sleep again - if a cpu makes a process runnable on an idle cpu, it must wake it up to reschedule
198 lines
5.7 KiB
C
198 lines
5.7 KiB
C
#ifndef __APIC_H__
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#define __APIC_H__
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#define APIC_ENABLE 0x100
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#define APIC_FOCUS_DISABLED (1 << 9)
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#define APIC_SIV 0xFF
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#define APIC_TDCR_2 0x00
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#define APIC_TDCR_4 0x01
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#define APIC_TDCR_8 0x02
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#define APIC_TDCR_16 0x03
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#define APIC_TDCR_32 0x08
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#define APIC_TDCR_64 0x09
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#define APIC_TDCR_128 0x0a
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#define APIC_TDCR_1 0x0b
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#define APIC_LVTT_VECTOR_MASK 0x000000FF
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#define APIC_LVTT_DS_PENDING (1 << 12)
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#define APIC_LVTT_MASK (1 << 16)
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#define APIC_LVTT_TM (1 << 17)
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#define APIC_LVT_IIPP_MASK 0x00002000
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#define APIC_LVT_IIPP_AH 0x00002000
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#define APIC_LVT_IIPP_AL 0x00000000
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#define IOAPIC_REGSEL 0x0
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#define IOAPIC_RW 0x10
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#define APIC_ICR_DM_MASK 0x00000700
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#define APIC_ICR_VECTOR APIC_LVTT_VECTOR_MASK
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#define APIC_ICR_DM_FIXED (0 << 8)
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#define APIC_ICR_DM_LOWEST_PRIORITY (1 << 8)
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#define APIC_ICR_DM_SMI (2 << 8)
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#define APIC_ICR_DM_RESERVED (3 << 8)
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#define APIC_ICR_DM_NMI (4 << 8)
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#define APIC_ICR_DM_INIT (5 << 8)
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#define APIC_ICR_DM_STARTUP (6 << 8)
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#define APIC_ICR_DM_EXTINT (7 << 8)
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#define APIC_ICR_DM_PHYSICAL (0 << 11)
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#define APIC_ICR_DM_LOGICAL (1 << 11)
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#define APIC_ICR_DELIVERY_PENDING (1 << 12)
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#define APIC_ICR_INT_POLARITY (1 << 13)
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#define APIC_ICR_LEVEL_ASSERT (1 << 14)
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#define APIC_ICR_LEVEL_DEASSERT (0 << 14)
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#define APIC_ICR_TRIGGER (1 << 15)
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#define APIC_ICR_INT_MASK (1 << 16)
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#define APIC_ICR_DEST_FIELD (0 << 18)
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#define APIC_ICR_DEST_SELF (1 << 18)
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#define APIC_ICR_DEST_ALL (2 << 18)
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#define APIC_ICR_DEST_ALL_BUT_SELF (3 << 18)
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#define LOCAL_APIC_DEF_ADDR 0xfee00000 /* default local apic address */
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#define IO_APIC_DEF_ADDR 0xfec00000 /* default i/o apic address */
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#define LAPIC_ID (lapic_addr + 0x020)
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#define LAPIC_VERSION (lapic_addr + 0x030)
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#define LAPIC_TPR (lapic_addr + 0x080)
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#define LAPIC_EOI (lapic_addr + 0x0b0)
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#define LAPIC_LDR (lapic_addr + 0x0d0)
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#define LAPIC_DFR (lapic_addr + 0x0e0)
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#define LAPIC_SIVR (lapic_addr + 0x0f0)
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#define LAPIC_ISR (lapic_addr + 0x100)
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#define LAPIC_TMR (lapic_addr + 0x180)
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#define LAPIC_IRR (lapic_addr + 0x200)
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#define LAPIC_ESR (lapic_addr + 0x280)
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#define LAPIC_ICR1 (lapic_addr + 0x300)
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#define LAPIC_ICR2 (lapic_addr + 0x310)
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#define LAPIC_LVTTR (lapic_addr + 0x320)
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#define LAPIC_LVTTMR (lapic_addr + 0x330)
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#define LAPIC_LVTPCR (lapic_addr + 0x340)
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#define LAPIC_LINT0 (lapic_addr + 0x350)
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#define LAPIC_LINT1 (lapic_addr + 0x360)
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#define LAPIC_LVTER (lapic_addr + 0x370)
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#define LAPIC_TIMER_ICR (lapic_addr + 0x380)
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#define LAPIC_TIMER_CCR (lapic_addr + 0x390)
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#define LAPIC_TIMER_DCR (lapic_addr + 0x3e0)
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#define IOAPIC_ID 0x0
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#define IOAPIC_VERSION 0x1
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#define IOAPIC_ARB 0x2
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#define IOAPIC_REDIR_TABLE 0x10
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#define APIC_TIMER_INT_VECTOR 0xf0
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#define APIC_SMP_SCHED_PROC_VECTOR 0xf1
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#define APIC_SMP_CPU_HALT_VECTOR 0xf2
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#define APIC_ERROR_INT_VECTOR 0xfe
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#define APIC_SPURIOUS_INT_VECTOR 0xff
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#ifndef __ASSEMBLY__
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#include "kernel/kernel.h"
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EXTERN vir_bytes lapic_addr;
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EXTERN vir_bytes lapic_eoi_addr;
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EXTERN int ioapic_enabled;
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EXTERN int bsp_lapic_id;
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#define MAX_NR_IOAPICS 32
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#define MAX_IOAPIC_IRQS 64
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EXTERN int ioapic_enabled;
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struct io_apic {
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unsigned id;
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vir_bytes addr; /* presently used address */
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phys_bytes paddr; /* where is it inphys space */
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vir_bytes vaddr; /* adress after paging s on */
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unsigned pins;
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unsigned gsi_base;
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};
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EXTERN struct io_apic io_apic[MAX_NR_IOAPICS];
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EXTERN unsigned nioapics;
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EXTERN u32_t lapic_addr_vaddr; /* we remember the virtual address here until we
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switch to paging */
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_PROTOTYPE (int lapic_enable, (unsigned cpu));
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EXTERN int ioapic_enabled;
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EXTERN unsigned nioapics;
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_PROTOTYPE (void lapic_microsec_sleep, (unsigned count));
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_PROTOTYPE (void ioapic_disable_irqs, (u32_t irqs));
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_PROTOTYPE (void ioapic_enable_irqs, (u32_t irqs));
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_PROTOTYPE (int lapic_enable, (unsigned cpu));
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_PROTOTYPE (void lapic_disable, (void));
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_PROTOTYPE (void ioapic_disable_all, (void));
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_PROTOTYPE (int ioapic_enable_all, (void));
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_PROTOTYPE(int detect_ioapics, (void));
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_PROTOTYPE(void apic_idt_init, (int reset));
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#ifdef CONFIG_SMP
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_PROTOTYPE(int apic_send_startup_ipi, (unsigned cpu, phys_bytes trampoline));
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_PROTOTYPE(int apic_send_init_ipi, (unsigned cpu, phys_bytes trampoline));
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_PROTOTYPE(unsigned int apicid, (void));
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_PROTOTYPE(void ioapic_set_id, (u32_t addr, unsigned int id));
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#else
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_PROTOTYPE(int apic_single_cpu_init, (void));
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#endif
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_PROTOTYPE(void lapic_set_timer_periodic, (const unsigned freq));
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_PROTOTYPE(void lapic_set_timer_one_shot, (const u32_t value));
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_PROTOTYPE(void lapic_stop_timer, (void));
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_PROTOTYPE(void lapic_restart_timer, (void));
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_PROTOTYPE(void ioapic_set_irq, (unsigned irq));
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_PROTOTYPE(void ioapic_unset_irq, (unsigned irq));
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/* signal the end of interrupt handler to apic */
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#define apic_eoi() do { *((volatile u32_t *) lapic_eoi_addr) = 0; } while(0)
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_PROTOTYPE(void ioapic_eoi, (int irq));
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_PROTOTYPE(void dump_apic_irq_state, (void));
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_PROTOTYPE(void apic_send_ipi, (unsigned vector, unsigned cpu, int type));
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_PROTOTYPE(void apic_ipi_sched_intr, (void));
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_PROTOTYPE(void apic_ipi_halt_intr, (void));
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#define APIC_IPI_DEST 0
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#define APIC_IPI_SELF 1
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#define APIC_IPI_TO_ALL 2
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#define APIC_IPI_TO_ALL_BUT_SELF 3
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#define apic_send_ipi_single(vector,cpu) \
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apic_send_ipi(vector, cpu, APIC_IPI_DEST);
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#define apic_send_ipi_self(vector) \
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apic_send_ipi(vector, 0, APIC_IPI_SELF)
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#define apic_send_ipi_all(vector) \
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apic_send_ipi (vector, 0, APIC_IPI_TO_ALL)
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#define apic_send_ipi_allbutself(vector) \
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apic_send_ipi (vector, 0, APIC_IPI_TO_ALL_BUT_SELF);
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#include <minix/cpufeature.h>
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#define cpu_feature_apic_on_chip() _cpufeature(_CPUF_I386_APIC_ON_CHIP)
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#define lapic_read(what) (*((volatile u32_t *)((what))))
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#define lapic_write(what, data) do { \
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(*((volatile u32_t *)((what)))) = data; \
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} while(0)
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#endif /* __ASSEMBLY__ */
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#endif /* __APIC_H__ */
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