1f9ce647cf
Move archtypes.h to include/ dir, since several servers require it. Move fpu.h and stackframe.h to arch-specific header directory. Make source files and makefiles aware of the new header locations.
479 lines
10 KiB
C
479 lines
10 KiB
C
/* system dependent functions for use inside the whole kernel. */
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#include "../../kernel.h"
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#include <unistd.h>
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#include <ctype.h>
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#include <string.h>
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#include <machine/cmos.h>
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#include <machine/bios.h>
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#include <minix/portio.h>
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#include <minix/cpufeature.h>
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#include <a.out.h>
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#include "archconst.h"
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#include "proto.h"
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#include "../../proc.h"
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#include "../../debug.h"
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#ifdef CONFIG_APIC
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#include "apic.h"
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#endif
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/* set MP and NE flags to handle FPU exceptions in native mode. */
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#define CR0_MP_NE 0x0022
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/* set CR4.OSFXSR[bit 9] if FXSR is supported. */
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#define CR4_OSFXSR (1L<<9)
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/* set OSXMMEXCPT[bit 10] if we provide #XM handler. */
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#define CR4_OSXMMEXCPT (1L<<10)
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FORWARD _PROTOTYPE( void ser_debug, (int c));
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PUBLIC void arch_monitor(void)
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{
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monitor();
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}
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PUBLIC int cpu_has_tsc;
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PUBLIC void arch_shutdown(int how)
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{
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/* Mask all interrupts, including the clock. */
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outb( INT_CTLMASK, ~0);
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if(minix_panicing) {
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/* We're panicing? Then retrieve and decode currently
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* loaded segment selectors.
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*/
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printseg("cs: ", 1, proc_ptr, read_cs());
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printseg("ds: ", 0, proc_ptr, read_ds());
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if(read_ds() != read_ss()) {
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printseg("ss: ", 0, NULL, read_ss());
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}
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}
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if(how != RBT_RESET) {
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/* return to boot monitor */
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outb( INT_CTLMASK, 0);
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outb( INT2_CTLMASK, 0);
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/* Return to the boot monitor. Set
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* the program if not already done.
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*/
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if (how != RBT_MONITOR)
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arch_set_params("", 1);
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if(minix_panicing) {
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int source, dest;
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static char mybuffer[sizeof(params_buffer)];
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char *lead = "echo \\n*** kernel messages:\\n";
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int leadlen = strlen(lead);
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strcpy(mybuffer, lead);
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#define DECSOURCE source = (source - 1 + _KMESS_BUF_SIZE) % _KMESS_BUF_SIZE
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dest = sizeof(mybuffer)-1;
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mybuffer[dest--] = '\0';
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source = kmess.km_next;
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DECSOURCE;
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while(dest >= leadlen) {
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char c = kmess.km_buf[source];
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if(c == '\n') {
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mybuffer[dest--] = 'n';
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mybuffer[dest] = '\\';
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} else if(isprint(c) &&
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c != '\'' && c != '"' &&
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c != '\\' && c != ';') {
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mybuffer[dest] = c;
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} else mybuffer[dest] = ' ';
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DECSOURCE;
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dest--;
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}
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arch_set_params(mybuffer, strlen(mybuffer)+1);
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}
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arch_monitor();
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} else {
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/* Reset the system by forcing a processor shutdown. First stop
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* the BIOS memory test by setting a soft reset flag.
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*/
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u16_t magic = STOP_MEM_CHECK;
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phys_copy(vir2phys(&magic), SOFT_RESET_FLAG_ADDR,
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SOFT_RESET_FLAG_SIZE);
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reset();
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}
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}
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/* address of a.out headers, set in mpx386.s */
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phys_bytes aout;
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PUBLIC void arch_get_aout_headers(int i, struct exec *h)
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{
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/* The bootstrap loader created an array of the a.out headers at
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* absolute address 'aout'. Get one element to h.
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*/
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phys_copy(aout + i * A_MINHDR, vir2phys(h), (phys_bytes) A_MINHDR);
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}
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PRIVATE void tss_init(struct tss_s * tss, void * kernel_stack, unsigned cpu)
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{
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/*
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* make space for process pointer and cpu id and point to the first
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* usable word
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*/
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tss->sp0 = ((unsigned) kernel_stack) - 2 * sizeof(void *);
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tss->ss0 = DS_SELECTOR;
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/*
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* set the cpu id at the top of the stack so we know on which cpu is
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* this stak in use when we trap to kernel
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*/
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*((reg_t *)(tss->sp0 + 1 * sizeof(reg_t))) = cpu;
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}
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PUBLIC void arch_init(void)
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{
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unsigned short cw, sw;
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fninit();
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sw = fnstsw();
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fnstcw(&cw);
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if((sw & 0xff) == 0 &&
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(cw & 0x103f) == 0x3f) {
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/* We have some sort of FPU, but don't check exact model.
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* Set CR0_NE and CR0_MP to handle fpu exceptions
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* in native mode. */
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write_cr0(read_cr0() | CR0_MP_NE);
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fpu_presence = 1;
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if(_cpufeature(_CPUF_I386_FXSR)) {
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register struct proc *rp;
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phys_bytes aligned_fp_area;
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/* Enable FXSR feature usage. */
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write_cr4(read_cr4() | CR4_OSFXSR | CR4_OSXMMEXCPT);
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osfxsr_feature = 1;
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for (rp = BEG_PROC_ADDR; rp < END_PROC_ADDR; ++rp) {
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/* FXSR requires 16-byte alignment of memory
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* image, but unfortunately some old tools
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* (probably linker) ignores ".balign 16"
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* applied to our memory image.
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* Thus we have to do manual alignment.
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*/
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aligned_fp_area =
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(phys_bytes) &rp->p_fpu_state.fpu_image;
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if(aligned_fp_area % FPUALIGN) {
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aligned_fp_area += FPUALIGN -
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(aligned_fp_area % FPUALIGN);
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}
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rp->p_fpu_state.fpu_save_area_p =
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(void *) aligned_fp_area;
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}
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} else {
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osfxsr_feature = 0;
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}
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} else {
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/* No FPU presents. */
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fpu_presence = 0;
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osfxsr_feature = 0;
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return;
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}
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#ifdef CONFIG_APIC
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/*
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* this is setting kernel segments to cover most of the phys memory. The
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* value is high enough to reach local APIC nad IOAPICs before paging is
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* turned on.
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*/
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prot_set_kern_seg_limit(0xfff00000);
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reload_ds();
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#endif
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idt_init();
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tss_init(&tss, &k_boot_stktop, 0);
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#if defined(CONFIG_APIC) && !defined(CONFIG_SMP)
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if (config_no_apic) {
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BOOT_VERBOSE(printf("APIC disabled, using legacy PIC\n"));
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}
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else if (!apic_single_cpu_init()) {
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BOOT_VERBOSE(printf("APIC not present, using legacy PIC\n"));
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}
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#endif
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}
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#define COM1_BASE 0x3F8
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#define COM1_THR (COM1_BASE + 0)
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#define COM1_RBR (COM1_BASE + 0)
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#define COM1_LSR (COM1_BASE + 5)
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#define LSR_DR 0x01
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#define LSR_THRE 0x20
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PUBLIC void ser_putc(char c)
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{
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int i;
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int lsr, thr;
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lsr= COM1_LSR;
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thr= COM1_THR;
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for (i= 0; i<100000; i++)
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{
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if (inb( lsr) & LSR_THRE)
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break;
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}
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outb( thr, c);
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}
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/*===========================================================================*
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* do_ser_debug *
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*===========================================================================*/
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PUBLIC void do_ser_debug()
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{
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u8_t c, lsr;
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lsr= inb(COM1_LSR);
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if (!(lsr & LSR_DR))
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return;
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c = inb(COM1_RBR);
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ser_debug(c);
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}
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PRIVATE void ser_dump_queues(void)
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{
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int q;
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for(q = 0; q < NR_SCHED_QUEUES; q++) {
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struct proc *p;
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if(rdy_head[q])
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printf("%2d: ", q);
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for(p = rdy_head[q]; p; p = p->p_nextready) {
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printf("%s / %d ", p->p_name, p->p_endpoint);
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}
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printf("\n");
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}
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}
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PRIVATE void ser_dump_segs(void)
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{
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struct proc *pp;
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for (pp= BEG_PROC_ADDR; pp < END_PROC_ADDR; pp++)
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{
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if (isemptyp(pp))
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continue;
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printf("%d: %s ep %d\n", proc_nr(pp), pp->p_name, pp->p_endpoint);
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printseg("cs: ", 1, pp, pp->p_reg.cs);
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printseg("ds: ", 0, pp, pp->p_reg.ds);
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if(pp->p_reg.ss != pp->p_reg.ds) {
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printseg("ss: ", 0, pp, pp->p_reg.ss);
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}
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}
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}
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PRIVATE void ser_debug(int c)
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{
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serial_debug_active = 1;
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switch(c)
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{
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case 'Q':
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minix_shutdown(NULL);
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NOT_REACHABLE;
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case '1':
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ser_dump_proc();
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break;
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case '2':
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ser_dump_queues();
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break;
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case '3':
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ser_dump_segs();
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break;
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#if DEBUG_TRACE
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#define TOGGLECASE(ch, flag) \
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case ch: { \
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if(verboseflags & flag) { \
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verboseflags &= ~flag; \
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printf("%s disabled\n", #flag); \
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} else { \
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verboseflags |= flag; \
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printf("%s enabled\n", #flag); \
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} \
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break; \
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}
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TOGGLECASE('8', VF_SCHEDULING)
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TOGGLECASE('9', VF_PICKPROC)
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#endif
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}
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serial_debug_active = 0;
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}
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PRIVATE void printslot(struct proc *pp, int level)
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{
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struct proc *depproc = NULL;
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endpoint_t dep;
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#define COL { int i; for(i = 0; i < level; i++) printf("> "); }
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if(level >= NR_PROCS) {
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printf("loop??\n");
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return;
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}
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COL
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printf("%d: %s %d prio %d/%d time %d/%d cycles 0x%x%08x cr3 0x%lx rts %s misc %s",
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proc_nr(pp), pp->p_name, pp->p_endpoint,
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pp->p_priority, pp->p_max_priority, pp->p_user_time,
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pp->p_sys_time, pp->p_cycles.hi, pp->p_cycles.lo, pp->p_seg.p_cr3,
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rtsflagstr(pp->p_rts_flags), miscflagstr(pp->p_misc_flags));
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if((dep = P_BLOCKEDON(pp)) != NONE) {
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printf(" blocked on: ");
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if(dep == ANY) {
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printf(" ANY\n");
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} else {
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int procno;
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if(!isokendpt(dep, &procno)) {
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printf(" ??? %d\n", dep);
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} else {
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depproc = proc_addr(procno);
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if(isemptyp(depproc)) {
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printf(" empty slot %d???\n", procno);
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depproc = NULL;
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} else {
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printf(" %s\n", depproc->p_name);
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}
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}
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}
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} else {
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printf("\n");
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}
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COL
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proc_stacktrace(pp);
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if(depproc)
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printslot(depproc, level+1);
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}
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PUBLIC void ser_dump_proc()
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{
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struct proc *pp;
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for (pp= BEG_PROC_ADDR; pp < END_PROC_ADDR; pp++)
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{
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if (isemptyp(pp))
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continue;
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printslot(pp, 0);
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}
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}
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#if SPROFILE
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PUBLIC int arch_init_profile_clock(u32_t freq)
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{
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int r;
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/* Set CMOS timer frequency. */
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outb(RTC_INDEX, RTC_REG_A);
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outb(RTC_IO, RTC_A_DV_OK | freq);
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/* Enable CMOS timer interrupts. */
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outb(RTC_INDEX, RTC_REG_B);
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r = inb(RTC_IO);
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outb(RTC_INDEX, RTC_REG_B);
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outb(RTC_IO, r | RTC_B_PIE);
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/* Mandatory read of CMOS register to enable timer interrupts. */
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outb(RTC_INDEX, RTC_REG_C);
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inb(RTC_IO);
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return CMOS_CLOCK_IRQ;
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}
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PUBLIC void arch_stop_profile_clock(void)
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{
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int r;
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/* Disable CMOS timer interrupts. */
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outb(RTC_INDEX, RTC_REG_B);
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r = inb(RTC_IO);
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outb(RTC_INDEX, RTC_REG_B);
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outb(RTC_IO, r & ~RTC_B_PIE);
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}
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PUBLIC void arch_ack_profile_clock(void)
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{
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/* Mandatory read of CMOS register to re-enable timer interrupts. */
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outb(RTC_INDEX, RTC_REG_C);
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inb(RTC_IO);
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}
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#endif
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#define COLOR_BASE 0xB8000L
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PRIVATE void cons_setc(int pos, int c)
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{
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char ch;
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ch= c;
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phys_copy(vir2phys((vir_bytes)&ch), COLOR_BASE+(20*80+pos)*2, 1);
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}
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PRIVATE void cons_seth(int pos, int n)
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{
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n &= 0xf;
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if (n < 10)
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cons_setc(pos, '0'+n);
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else
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cons_setc(pos, 'A'+(n-10));
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}
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/* Saved by mpx386.s into these variables. */
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u32_t params_size, params_offset, mon_ds;
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PUBLIC int arch_get_params(char *params, int maxsize)
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{
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phys_copy(seg2phys(mon_ds) + params_offset, vir2phys(params),
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MIN(maxsize, params_size));
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params[maxsize-1] = '\0';
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return OK;
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}
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PUBLIC int arch_set_params(char *params, int size)
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{
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if(size > params_size)
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return E2BIG;
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phys_copy(vir2phys(params), seg2phys(mon_ds) + params_offset, size);
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return OK;
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}
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PUBLIC void arch_do_syscall(struct proc *proc)
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{
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/* Perform a previously postponed system call.
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*/
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int call_nr, src_dst_e;
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message *m_ptr;
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long bit_map;
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/* Get the system call parameters from their respective registers. */
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call_nr = proc->p_reg.cx;
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src_dst_e = proc->p_reg.retreg;
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m_ptr = (message *) proc->p_reg.bx;
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bit_map = proc->p_reg.dx;
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/* Make the system call, for real this time. */
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proc->p_reg.retreg = do_ipc(call_nr, src_dst_e, m_ptr, bit_map);
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}
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PUBLIC struct proc * arch_finish_schedcheck(void)
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{
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char * stk;
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stk = (char *)tss.sp0;
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/* set pointer to the process to run on the stack */
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*((reg_t *)stk) = (reg_t) proc_ptr;
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return proc_ptr;
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}
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