c8f3b10909
. also disable stack protection feature for gcc, causes build errors for pkgsrc gcc on minix Change-Id: I1c6e2bcb4d948098d642543d7b2711284ee55c72
305 lines
8 KiB
C
305 lines
8 KiB
C
#include "kernel/kernel.h"
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#include "kernel/clock.h"
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#include <sys/types.h>
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#include <machine/cpu.h>
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#include <minix/mmio.h>
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#include <assert.h>
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#include <io.h>
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#include <stdlib.h>
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#include <stdio.h>
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#include "arch_proto.h"
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#include "omap_timer.h"
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#include "omap_intr.h"
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static irq_hook_t omap3_timer_hook; /* interrupt handler hook */
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static u64_t high_frc;
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struct omap_timer_registers;
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struct omap_timer {
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vir_bytes base;
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int irq_nr;
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struct omap_timer_registers *regs;
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};
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struct omap_timer_registers {
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vir_bytes TIDR;
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vir_bytes TIOCP_CFG;
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vir_bytes TISTAT;
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vir_bytes TISR;
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vir_bytes TIER;
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vir_bytes TWER;
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vir_bytes TCLR;
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vir_bytes TCRR;
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vir_bytes TLDR;
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vir_bytes TTGR;
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vir_bytes TWPS;
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vir_bytes TMAR;
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vir_bytes TCAR1;
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vir_bytes TSICR;
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vir_bytes TCAR2;
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vir_bytes TPIR;
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vir_bytes TNIR;
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vir_bytes TCVR;
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vir_bytes TOCR;
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vir_bytes TOWR;
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};
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static struct omap_timer_registers regs_v1 = {
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.TIDR = OMAP3_TIMER_TIDR,
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.TIOCP_CFG = OMAP3_TIMER_TIOCP_CFG,
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.TISTAT = OMAP3_TIMER_TISTAT,
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.TISR = OMAP3_TIMER_TISR,
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.TIER = OMAP3_TIMER_TIER,
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.TWER = OMAP3_TIMER_TWER,
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.TCLR = OMAP3_TIMER_TCLR,
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.TCRR = OMAP3_TIMER_TCRR,
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.TLDR = OMAP3_TIMER_TLDR,
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.TTGR = OMAP3_TIMER_TTGR,
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.TWPS = OMAP3_TIMER_TWPS,
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.TMAR = OMAP3_TIMER_TMAR,
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.TCAR1 = OMAP3_TIMER_TCAR1,
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.TSICR = OMAP3_TIMER_TSICR,
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.TCAR2 = OMAP3_TIMER_TCAR2,
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.TPIR = OMAP3_TIMER_TPIR,
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.TNIR = OMAP3_TIMER_TNIR,
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.TCVR = OMAP3_TIMER_TCVR,
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.TOCR = OMAP3_TIMER_TOCR,
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.TOWR = OMAP3_TIMER_TOWR,
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};
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#ifdef DM37XX
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static struct omap_timer timer = {
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.base = OMAP3_GPTIMER1_BASE,
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.irq_nr = OMAP3_GPT1_IRQ,
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.regs = ®s_v1
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};
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/* free running timer */
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static struct omap_timer fr_timer = {
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.base = OMAP3_GPTIMER10_BASE,
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.irq_nr = OMAP3_GPT10_IRQ,
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.regs = ®s_v1
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};
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#endif
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#ifdef AM335X
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/* AM335X has a different ip block for the non
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1ms timers */
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static struct omap_timer_registers regs_v2 = {
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.TIDR = AM335X_TIMER_TIDR,
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.TIOCP_CFG = AM335X_TIMER_TIOCP_CFG,
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.TISTAT = AM335X_TIMER_IRQSTATUS_RAW,
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.TISR = AM335X_TIMER_IRQSTATUS,
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.TIER = AM335X_TIMER_IRQENABLE_SET,
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.TWER = AM335X_TIMER_IRQWAKEEN,
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.TCLR = AM335X_TIMER_TCLR,
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.TCRR = AM335X_TIMER_TCRR,
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.TLDR = AM335X_TIMER_TLDR,
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.TTGR = AM335X_TIMER_TTGR,
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.TWPS = AM335X_TIMER_TWPS,
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.TMAR = AM335X_TIMER_TMAR,
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.TCAR1 = AM335X_TIMER_TCAR1,
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.TSICR = AM335X_TIMER_TSICR,
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.TCAR2 = AM335X_TIMER_TCAR2,
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.TPIR = -1 , /* UNDEF */
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.TNIR = -1 , /* UNDEF */
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.TCVR = -1 , /* UNDEF */
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.TOCR = -1 , /* UNDEF */
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.TOWR = -1 /* UNDEF */
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};
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/* normal timer */
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static struct omap_timer timer = {
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.base = AM335X_DMTIMER1_1MS_BASE,
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.irq_nr = AM335X_INT_TINT1_1MS,
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.regs = ®s_v1
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};
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/* free running timer */
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static struct omap_timer fr_timer = {
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.base = AM335X_DMTIMER7_BASE,
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.irq_nr = AM335X_INT_TINT7,
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.regs = ®s_v2
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};
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#endif
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static int done = 0;
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int omap3_register_timer_handler(const irq_handler_t handler)
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{
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/* Initialize the CLOCK's interrupt hook. */
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omap3_timer_hook.proc_nr_e = NONE;
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omap3_timer_hook.irq = timer.irq_nr;
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put_irq_handler(&omap3_timer_hook, timer.irq_nr, handler);
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return 0;
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}
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/* meta data for remapping */
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static kern_phys_map timer_phys_map;
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static kern_phys_map fr_timer_phys_map;
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void omap3_frclock_init(void)
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{
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u32_t tisr;
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kern_phys_map_ptr(fr_timer.base,ARM_PAGE_SIZE,
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&fr_timer_phys_map, (vir_bytes) &fr_timer.base);
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/* enable the clock */
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#ifdef AM335X
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/* Disable the module and wait for the module to be disabled */
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set32(CM_PER_TIMER7_CLKCTRL, CM_MODULEMODE_MASK,CM_MODULEMODE_DISABLED);
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while( (mmio_read(CM_PER_TIMER7_CLKCTRL) & CM_CLKCTRL_IDLEST) != CM_CLKCTRL_IDLEST_DISABLE);
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set32(CLKSEL_TIMER7_CLK,CLKSEL_TIMER7_CLK_SEL_MASK, CLKSEL_TIMER7_CLK_SEL_SEL2);
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while( (read32(CLKSEL_TIMER7_CLK) & CLKSEL_TIMER7_CLK_SEL_MASK) != CLKSEL_TIMER7_CLK_SEL_SEL2);
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/* enable the module and wait for the module to be ready */
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set32(CM_PER_TIMER7_CLKCTRL,CM_MODULEMODE_MASK,CM_MODULEMODE_ENABLE);
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while( (mmio_read(CM_PER_TIMER7_CLKCTRL) & CM_CLKCTRL_IDLEST) != CM_CLKCTRL_IDLEST_FUNC);
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#endif
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/* Stop timer */
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mmio_clear(fr_timer.base + fr_timer.regs->TCLR, OMAP3_TCLR_ST);
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#ifdef DM37XX
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/* Use functional clock source for GPTIMER10 */
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mmio_set(OMAP3_CM_CLKSEL_CORE, OMAP3_CLKSEL_GPT10);
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#endif
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#ifdef DM37XX
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/* Scale timer down to 13/8 = 1.625 Mhz to roughly get microsecond ticks */
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/* The scale is computed as 2^(PTV+1). So if PTV == 2, we get 2^3 = 8.
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*/
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mmio_set(fr_timer.base + fr_timer.regs->TCLR, (2 << OMAP3_TCLR_PTV));
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#endif
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#ifdef AM335X
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/* 24Mhz / 16 = 1.5 Mhz */
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mmio_set(fr_timer.base + fr_timer.regs->TCLR, (3 << OMAP3_TCLR_PTV));
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#endif
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/* Start and auto-reload at 0 */
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mmio_write(fr_timer.base + fr_timer.regs->TLDR, 0x0);
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mmio_write(fr_timer.base + fr_timer.regs->TCRR, 0x0);
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/* Set up overflow interrupt */
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tisr = OMAP3_TISR_MAT_IT_FLAG | OMAP3_TISR_OVF_IT_FLAG |
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OMAP3_TISR_TCAR_IT_FLAG;
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mmio_write(fr_timer.base + fr_timer.regs->TISR, tisr); /* Clear interrupt status */
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mmio_write(fr_timer.base + fr_timer.regs->TIER, OMAP3_TIER_OVF_IT_ENA);
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/* Start timer */
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mmio_set(fr_timer.base + fr_timer.regs->TCLR,
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OMAP3_TCLR_OVF_TRG|OMAP3_TCLR_AR|OMAP3_TCLR_ST|OMAP3_TCLR_PRE);
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done = 1;
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}
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void omap3_frclock_stop()
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{
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mmio_clear(fr_timer.base + fr_timer.regs->TCLR, OMAP3_TCLR_ST);
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}
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void omap3_timer_init(unsigned freq)
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{
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u32_t tisr;
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kern_phys_map_ptr(timer.base,ARM_PAGE_SIZE,
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&timer_phys_map, (vir_bytes) &timer.base);
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#ifdef AM335X
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/* disable the module and wait for the module to be disabled */
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set32(CM_WKUP_TIMER1_CLKCTRL, CM_MODULEMODE_MASK,CM_MODULEMODE_DISABLED);
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while( (mmio_read(CM_WKUP_TIMER1_CLKCTRL) & CM_CLKCTRL_IDLEST) != CM_CLKCTRL_IDLEST_DISABLE);
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set32(CLKSEL_TIMER1MS_CLK,CLKSEL_TIMER1MS_CLK_SEL_MASK, CLKSEL_TIMER1MS_CLK_SEL_SEL2);
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while( (read32(CLKSEL_TIMER1MS_CLK) & CLKSEL_TIMER1MS_CLK_SEL_MASK) != CLKSEL_TIMER1MS_CLK_SEL_SEL2);
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/* enable the module and wait for the module to be ready */
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set32(CM_WKUP_TIMER1_CLKCTRL,CM_MODULEMODE_MASK,CM_MODULEMODE_ENABLE);
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while( (mmio_read(CM_WKUP_TIMER1_CLKCTRL) & CM_CLKCTRL_IDLEST) != CM_CLKCTRL_IDLEST_FUNC);
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#endif
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/* Stop timer */
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mmio_clear(timer.base + fr_timer.regs->TCLR, OMAP3_TCLR_ST);
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#ifdef DM37XX
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/* Use 32 KHz clock source for GPTIMER1 */
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mmio_clear(OMAP3_CM_CLKSEL_WKUP, OMAP3_CLKSEL_GPT1);
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#endif
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/* Use 1-ms tick mode for GPTIMER1 TRM 16.2.4.2.1 */
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mmio_write(timer.base + timer.regs->TPIR, 232000);
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mmio_write(timer.base + timer.regs->TNIR, -768000);
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mmio_write(timer.base + timer.regs->TLDR, 0xffffffe0);
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mmio_write(timer.base + timer.regs->TCRR, 0xffffffe0);
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/* Set up overflow interrupt */
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tisr = OMAP3_TISR_MAT_IT_FLAG | OMAP3_TISR_OVF_IT_FLAG |
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OMAP3_TISR_TCAR_IT_FLAG;
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mmio_write(timer.base + timer.regs->TISR, tisr); /* Clear interrupt status */
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mmio_write(timer.base + timer.regs->TIER, OMAP3_TIER_OVF_IT_ENA);
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omap3_irq_unmask(timer.irq_nr);
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/* Start timer */
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mmio_set(timer.base + timer.regs->TCLR,
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OMAP3_TCLR_OVF_TRG|OMAP3_TCLR_AR|OMAP3_TCLR_ST);
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}
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void omap3_timer_stop()
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{
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mmio_clear(timer.base + timer.regs->TCLR, OMAP3_TCLR_ST);
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}
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static u32_t read_frc(void)
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{
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if (done == 0)
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return 0;
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return mmio_read(fr_timer.base + fr_timer.regs->TCRR);
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}
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static void frc_overflow_check(void)
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{
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static int prev_frc_valid;
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static u32_t prev_frc;
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u32_t cur_frc = read_frc();
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if(prev_frc_valid && prev_frc > cur_frc)
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high_frc++;
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prev_frc = cur_frc;
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prev_frc_valid = 1;
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}
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void omap3_timer_int_handler()
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{
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/* Clear all interrupts */
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u32_t tisr;
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/* when the kernel itself is running interrupts are disabled.
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* We should therefore also read the overflow counter to detect
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* this as to not miss events.
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*/
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tisr = OMAP3_TISR_MAT_IT_FLAG | OMAP3_TISR_OVF_IT_FLAG |
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OMAP3_TISR_TCAR_IT_FLAG;
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mmio_write(timer.base + timer.regs->TISR, tisr);
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frc_overflow_check();
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}
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/* Use the free running clock as TSC */
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void read_tsc_64(u64_t *t)
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{
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u32_t now;
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frc_overflow_check();
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now = read_frc();
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*t = (u64_t) now + (high_frc << 32);
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}
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