7e11828c6e
Created a new directory called bsp (board support package) to hold board or system on chip specific code. The idea is the following. Change-Id: Ica5886806940facae2fa5492fcc938b3c2b989be
58 lines
1.4 KiB
C
58 lines
1.4 KiB
C
#include <sys/types.h>
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#include <machine/cpu.h>
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#include <minix/type.h>
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#include <minix/board.h>
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#include <io.h>
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#include "kernel/kernel.h"
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#include "kernel/proc.h"
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#include "kernel/vm.h"
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#include "kernel/proto.h"
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#include "arch_proto.h"
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#include "hw_intr.h"
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#include "omap_intr_registers.h"
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static struct omap_intr {
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vir_bytes base;
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int size;
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} omap_intr;
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static kern_phys_map intr_phys_map;
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int intr_init(const int auto_eoi)
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{
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if (BOARD_IS_BBXM(machine.board_id)) {
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omap_intr.base = OMAP3_DM37XX_INTR_BASE;
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} else if (BOARD_IS_BB(machine.board_id)) {
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omap_intr.base = OMAP3_AM335X_INTR_BASE;
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} else {
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panic("Can not do the interrupt setup. machine (0x%08x) is unknown\n",machine.board_id);
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};
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omap_intr.size = 0x1000 ; /* 4K */
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kern_phys_map_ptr(omap_intr.base,omap_intr.size,
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&intr_phys_map, (vir_bytes) &omap_intr.base);
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return 0;
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}
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void bsp_irq_handle(void) {
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/* Function called from assembly to handle interrupts */
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/* get irq */
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int irq = mmio_read(omap_intr.base + OMAP3_INTCPS_SIR_IRQ) & OMAP3_INTR_ACTIVEIRQ_MASK;
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/* handle irq */
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irq_handle(irq);
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/* re-enable. this should not trigger interrupts due to current cpsr state */
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mmio_write(omap_intr.base + OMAP3_INTCPS_CONTROL,OMAP3_INTR_NEWIRQAGR);
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}
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void bsp_irq_unmask(int irq)
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{
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mmio_write(OMAP3_INTR_MIR_CLEAR(omap_intr.base, irq >> 5), 1 << (irq & 0x1f));
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}
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void bsp_irq_mask(const int irq)
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{
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mmio_write(OMAP3_INTR_MIR_SET(omap_intr.base, irq >> 5), 1 << (irq & 0x1f));
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}
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