ba49a155b5
This patch introduces a framebuffer to Minix. It's written for the ARM port of Minix, but has an architectural split that separates the hardware dependent part from the non-hardware dependent part. Futhermore, this driver was developed using a screen that has a native resolution of 1024x600 pixels and having lack of support for obtaining EDID from the screen. Consequently, it uses a hardcoded resolution of 1024x600. The driver uses an interface based on the Linux ioctl API, but supports only a very limited subset.
272 lines
7.1 KiB
C
272 lines
7.1 KiB
C
/* Architecture dependent part for the framebuffer on the OMAP3. Since we don't
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* have support for EDID (which requires support for i2c, also something we
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* don't have, yet), but we do have a screen with 1024*600 resolution for our
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* testing purposes, we hardcode that resolution here. There's obvious room for
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* improvement. */
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#include <minix/chardriver.h>
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#include <minix/drivers.h>
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#include <minix/fb.h>
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#include <minix/type.h>
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#include <minix/vm.h>
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#include <assert.h>
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#include <sys/mman.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include "dss.h"
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#define SCREEN_WIDTH 1024
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#define SCREEN_HEIGHT 600
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#define PAGES_NR 2
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static vir_bytes dss_phys_base; /* Address of dss phys memory map */
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static vir_bytes dispc_phys_base; /* Address of dispc phys memory map */
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static vir_bytes fb_vir;
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static phys_bytes fb_phys;
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static size_t fb_size;
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static int initialized = 0;
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struct panel_config {
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u32_t timing_h;
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u32_t timing_v;
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u32_t pol_freq;
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u32_t divisor;
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u32_t lcd_size;
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u32_t panel_type;
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u32_t data_lines;
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u32_t load_mode;
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u32_t panel_color;
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};
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static const struct panel_config default_cfg = {
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/* See OMAP TRM section 15.7 for the register values/encoding */
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.timing_h = 0x1a4024c9, /* Horizontal timing */
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.timing_v = 0x02c00509, /* Vertical timing */
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.pol_freq = 0x00007028, /* Pol Freq */
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.divisor = 0x00010001, /* 96MHz Pixel Clock */
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.lcd_size = ((SCREEN_HEIGHT - 1) << 16 | (SCREEN_WIDTH - 1)),
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.panel_type = 0x01, /* TFT */
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.data_lines = 0x03, /* 24 Bit RGB */
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.load_mode = 0x02, /* Frame Mode */
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.panel_color = 0xFFFFFF /* WHITE */
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};
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static const struct fb_fix_screeninfo fbfs = {
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.xpanstep = 0,
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.ypanstep = 0,
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.ywrapstep = 0,
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.line_length = SCREEN_WIDTH * 4,
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.mmio_start = 0, /* Not implemented for char. special, so */
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.mmio_len = 0 /* these are set to 0 */
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};
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static struct fb_var_screeninfo fbvs = {
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.xres = SCREEN_WIDTH,
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.yres = SCREEN_HEIGHT,
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.xres_virtual = SCREEN_WIDTH,
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.yres_virtual = SCREEN_HEIGHT*2,
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.xoffset = 0,
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.yoffset = 0,
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.bits_per_pixel = 32,
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.red = {
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.offset = 16,
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.length = 8,
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.msb_right = 0
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},
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.green = {
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.offset = 8,
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.length = 8,
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.msb_right = 0
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},
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.blue = {
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.offset = 0,
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.length = 8,
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.msb_right = 0
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},
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.transp = {
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.offset = 24,
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.length = 8,
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.msb_right = 0
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}
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};
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static inline u32_t
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readw(vir_bytes addr)
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{
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return *((volatile u32_t *) addr);
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}
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static inline void
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writew(vir_bytes addr, u32_t val)
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{
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*((volatile u32_t *) addr) = val;
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}
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static void
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arch_configure_display(int minor)
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{
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/* Tell hardware where frame buffer is and turn display on */
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u32_t off, rdispc;
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if (!initialized) return;
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if (minor != 0) return;
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off = fbvs.yoffset * fbvs.xres_virtual * (fbvs.bits_per_pixel/8);
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writew((vir_bytes) OMAP3_DISPC_GFX_BA0(dispc_phys_base),
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fb_phys + (phys_bytes) off);
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rdispc = readw((vir_bytes) OMAP3_DISPC_CONTROL(dispc_phys_base));
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rdispc |= DISPC_LCDENABLE | DISPC_DIGITALENABLE | DISPC_GOLCD |
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DISPC_GODIGITAL | DISPC_GPOUT0 | DISPC_GPOUT1;
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writew((vir_bytes) OMAP3_DISPC_CONTROL(dispc_phys_base), rdispc);
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}
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int
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arch_get_device(int minor, struct device *dev)
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{
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if (!initialized) return ENXIO;
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if (minor != 0) return ENXIO;
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dev->dv_base = fb_vir;
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dev->dv_size = fb_size;
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return OK;
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}
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int
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arch_get_varscreeninfo(int minor, struct fb_var_screeninfo *fbvsp)
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{
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if (!initialized) return ENXIO;
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if (minor != 0) return ENXIO;
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*fbvsp = fbvs;
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return OK;
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}
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int
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arch_put_varscreeninfo(int minor, struct fb_var_screeninfo *fbvsp)
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{
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int r = OK;
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assert(fbvsp != NULL);
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if (!initialized) return ENXIO;
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if (minor != 0) return ENXIO;
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/* For now we only allow to play with the yoffset setting */
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if (fbvsp->yoffset != fbvs.yoffset) {
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if (fbvsp->yoffset < 0 || fbvsp->yoffset > fbvs.yres) {
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return EINVAL;
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}
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fbvs.yoffset = fbvsp->yoffset;
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}
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/* Now update hardware with new settings */
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arch_configure_display(minor);
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return OK;
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}
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int
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arch_get_fixscreeninfo(int minor, struct fb_fix_screeninfo *fbfsp)
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{
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if (!initialized) return ENXIO;
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if (minor != 0) return ENXIO;
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*fbfsp = fbfs;
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return OK;
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}
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int
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arch_pan_display(int minor, struct fb_var_screeninfo *fbvsp)
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{
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return arch_put_varscreeninfo(minor, fbvsp);
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}
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int
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arch_fb_init(int minor, struct device *dev)
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{
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u32_t rdispc;
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struct minix_mem_range mr;
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const struct panel_config *panel_cfg = &default_cfg;
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assert(dev != NULL);
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if (minor != 0) return ENXIO; /* We support only one minor */
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if (initialized) {
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dev->dv_base = fb_vir;
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dev->dv_size = fb_size;
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return OK;
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}
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initialized = 1;
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/* Configure DSS memory access */
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mr.mr_base = OMAP3_DSS_BASE;
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mr.mr_limit = mr.mr_base + 0x60;
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if (sys_privctl(SELF, SYS_PRIV_ADD_MEM, &mr) != OK) {
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panic("Unable to request access to DSS(1) memory");
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}
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dss_phys_base = (vir_bytes) vm_map_phys(SELF, (void *) OMAP3_DSS_BASE,
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0x60);
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if (dss_phys_base == (vir_bytes) MAP_FAILED) {
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panic("Unable to request access to DSS(2) memory");
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}
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/* Configure DISPC memory access */
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mr.mr_base = OMAP3_DISPC_BASE;
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mr.mr_limit = mr.mr_base + 0x430;
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if (sys_privctl(SELF, SYS_PRIV_ADD_MEM, &mr) != OK) {
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panic("Unable to request access to DISPC(1) memory");
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}
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dispc_phys_base = (vir_bytes) vm_map_phys(SELF,
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(void *) OMAP3_DISPC_BASE,
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0x430);
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if (dispc_phys_base == (vir_bytes) MAP_FAILED) {
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panic("Unable to request access to DISPC(2) memory");
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}
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/* Set timings, screen mode, screen size, etc. */
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writew(OMAP3_DISPC_TIMINGH(dispc_phys_base), panel_cfg->timing_h);
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writew(OMAP3_DISPC_TIMINGV(dispc_phys_base), panel_cfg->timing_v);
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writew(OMAP3_DISPC_POL_FREQ(dispc_phys_base), panel_cfg->pol_freq);
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writew(OMAP3_DISPC_DIVISOR(dispc_phys_base), panel_cfg->divisor);
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writew(OMAP3_DISPC_CONFIG(dispc_phys_base),
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panel_cfg->load_mode << LOADMODE_SHIFT);
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writew(OMAP3_DISPC_CONTROL(dispc_phys_base),
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panel_cfg->panel_type << TFTSTN_SHIFT |
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panel_cfg->data_lines << DATALINES_SHIFT);
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writew((vir_bytes) OMAP3_DISPC_SIZE_LCD(dispc_phys_base),
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panel_cfg->lcd_size);
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writew((vir_bytes) OMAP3_DISPC_GFX_SIZE(dispc_phys_base),
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panel_cfg->lcd_size);
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writew(OMAP3_DISPC_DEFAULT_COLOR0(dispc_phys_base),
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panel_cfg->panel_color);
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/* Enable gfx engine */
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writew(OMAP3_DISPC_GFX_ATTRIBUTES(dispc_phys_base),
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(DISPC_GFXBURSTSIZE_16 << GFXBURSTSIZE_SHIFT) |
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(DISPC_GFXFORMAT_RGB24 << GFXFORMAT_SHIFT) |
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(DISPC_GFXENABLE));
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writew(OMAP3_DISPC_GFX_ROW_INC(dispc_phys_base), 1);
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writew(OMAP3_DISPC_GFX_PIXEL_INC(dispc_phys_base), 1);
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/* Allocate contiguous physical memory for the display buffer */
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fb_size = fbvs.yres_virtual * fbvs.xres_virtual *
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(fbvs.bits_per_pixel / 8);
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fb_vir = (vir_bytes) alloc_contig(fb_size, 0, &fb_phys);
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if (fb_vir == (vir_bytes) MAP_FAILED) {
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panic("Unable to allocate contiguous memory\n");
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}
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dev->dv_base = fb_vir;
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dev->dv_size = fb_size;
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/* Configure buffer settings and turn on LCD/Digital */
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arch_configure_display(minor);
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return OK;
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}
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