264 lines
7.2 KiB
C
264 lines
7.2 KiB
C
#include "codec.h"
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/* Timeouts in milliseconds */
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#define WIP_TIMEOUT 250UL
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#define DRDY_TIMEOUT 250UL
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/* The default SRC syncronization state number is 1. This state occurs
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just after de-assertion of SYNC. This is supposed to be the safest
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state for accessing the codec with an ES1371 Rev 1. Later versions
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of the chip allegedly don't require syncronization. Be very careful
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if you change this ! */
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#define SRC_UNSYNCED 0xffffffffUL
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static u32_t SrcSyncState = 0x00010000UL;
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void CodecSetSrcSyncState (int state)
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{
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if (state < 0)
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SrcSyncState = SRC_UNSYNCED;
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else {
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SrcSyncState = (u32_t)state << 16;
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SrcSyncState &= 0x00070000Ul;
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}
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}
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int CodecWrite (DEV_STRUCT * pCC, u16_t wAddr, u16_t wData)
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{
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u32_t dtemp, i;
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u16_t wBaseAddr = pCC->base;
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/* wait for WIP bit (Write In Progress) to go away */
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/* remember, register CONC_dCODECCTL_OFF (0x14)
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is a pseudo read-write register */
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if (WaitBitd (wBaseAddr + CONC_dCODECCTL_OFF, 30, 0, WIP_TIMEOUT)){
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printf("CODEC_ERR_WIP_TIMEOUT\n");
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return (CODEC_ERR_WIP_TIMEOUT);
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}
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if (SRC_UNSYNCED != SrcSyncState)
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{
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/* enable SRC state data in SRC mux */
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if (WaitBitd (wBaseAddr + CONC_dSRCIO_OFF, SRC_BUSY_BIT, 0, 1000))
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return (CODEC_ERR_SRC_NOT_BUSY_TIMEOUT);
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/* todo: why are we writing an undefined register? */
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dtemp = pci_inl(wBaseAddr + CONC_dSRCIO_OFF);
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pci_outl(wBaseAddr + CONC_dSRCIO_OFF, (dtemp & SRC_CTLMASK) |
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0x00010000UL);
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/* wait for a SAFE time to write addr/data and then do it */
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/*_disable(); */
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for( i = 0; i < 0x1000UL; ++i )
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if( (pci_inl(wBaseAddr + CONC_dSRCIO_OFF) & 0x00070000UL) ==
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SrcSyncState )
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break;
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if (i >= 0x1000UL) {
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/* _enable(); */
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return (CODEC_ERR_SRC_SYNC_TIMEOUT);
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}
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}
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/* A test for 5880 - prime the PCI data bus */
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{
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u32_t dat = ((u32_t) wAddr << 16) | wData;
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char page = pci_inb(wBaseAddr + CONC_bMEMPAGE_OFF);
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pci_outl (wBaseAddr + CONC_bMEMPAGE_OFF, dat);
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/* write addr and data */
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pci_outl(wBaseAddr + CONC_dCODECCTL_OFF, dat);
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pci_outb(wBaseAddr + CONC_bMEMPAGE_OFF, page); /* restore page reg */
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}
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if (SRC_UNSYNCED != SrcSyncState)
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{
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/* _enable(); */
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/* restore SRC reg */
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if (WaitBitd (wBaseAddr + CONC_dSRCIO_OFF, SRC_BUSY_BIT, 0, 1000))
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return (CODEC_ERR_SRC_NOT_BUSY_TIMEOUT);
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pci_outl(wBaseAddr + CONC_dSRCIO_OFF, dtemp & 0xfff8ffffUL);
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}
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return 0;
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}
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int CodecRead (DEV_STRUCT * pCC, u16_t wAddr, u16_t *data)
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{
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u32_t dtemp, i;
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u16_t base = pCC->base;
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/* wait for WIP to go away */
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if (WaitBitd (base + CONC_dCODECCTL_OFF, 30, 0, WIP_TIMEOUT))
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return (CODEC_ERR_WIP_TIMEOUT);
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if (SRC_UNSYNCED != SrcSyncState)
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{
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/* enable SRC state data in SRC mux */
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if (WaitBitd (base + CONC_dSRCIO_OFF, SRC_BUSY_BIT, 0, 1000))
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return (CODEC_ERR_SRC_NOT_BUSY_TIMEOUT);
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dtemp = pci_inl(base + CONC_dSRCIO_OFF);
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pci_outl(base + CONC_dSRCIO_OFF, (dtemp & SRC_CTLMASK) |
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0x00010000UL);
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/* wait for a SAFE time to write a read request and then do it */
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/* todo: how do we solve the lock() problem? */
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/* _disable(); */
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for( i = 0; i < 0x1000UL; ++i )
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if( (pci_inl(base + CONC_dSRCIO_OFF) & 0x00070000UL) ==
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SrcSyncState )
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break;
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if (i >= 0x1000UL) {
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/*_enable();*/
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return (CODEC_ERR_SRC_SYNC_TIMEOUT);
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}
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}
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/* A test for 5880 - prime the PCI data bus */
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{
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/* set bit 23, this means read in stead of write. */
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u32_t dat = ((u32_t) wAddr << 16) | (1UL << 23);
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char page = pci_inb(base + CONC_bMEMPAGE_OFF);
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/* todo: why are we putting data in the mem page register??? */
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pci_outl(base + CONC_bMEMPAGE_OFF, dat);
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/* write addr w/data=0 and assert read request */
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pci_outl(base + CONC_dCODECCTL_OFF, dat);
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pci_outb(base + CONC_bMEMPAGE_OFF, page); /* restore page reg */
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}
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if (SRC_UNSYNCED != SrcSyncState)
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{
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/*_enable();*/
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/* restore SRC reg */
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if (WaitBitd (base + CONC_dSRCIO_OFF, SRC_BUSY_BIT, 0, 1000))
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return (CODEC_ERR_SRC_NOT_BUSY_TIMEOUT);
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pci_outl(base + CONC_dSRCIO_OFF, dtemp & 0xfff8ffffUL);
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}
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/* now wait for the stinkin' data (DRDY = data ready) */
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if (WaitBitd (base + CONC_dCODECCTL_OFF, 31, 1, DRDY_TIMEOUT))
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return (CODEC_ERR_DATA_TIMEOUT);
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dtemp = pci_inl(base + CONC_dCODECCTL_OFF);
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if (data)
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*data = (u16_t) dtemp;
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return 0;
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}
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int CodecWriteUnsynced (DEV_STRUCT * pCC, u16_t wAddr, u16_t wData)
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{
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/* wait for WIP to go away */
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if (WaitBitd (pCC->base + CONC_dCODECCTL_OFF, 30, 0, WIP_TIMEOUT))
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return (CODEC_ERR_WIP_TIMEOUT);
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/* write addr and data */
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pci_outl(pCC->base + CONC_dCODECCTL_OFF, ((u32_t) wAddr << 16) | wData);
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return 0;
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}
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int CodecReadUnsynced (DEV_STRUCT * pCC, u16_t wAddr, u16_t *data)
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{
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u32_t dtemp;
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/* wait for WIP to go away */
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if (WaitBitd (pCC->base + CONC_dCODECCTL_OFF, 30, 0, WIP_TIMEOUT))
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return (CODEC_ERR_WIP_TIMEOUT);
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/* write addr w/data=0 and assert read request */
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pci_outl(pCC->base + CONC_dCODECCTL_OFF, ((u32_t) wAddr << 16) | (1UL << 23));
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/* now wait for the stinkin' data (RDY) */
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if (WaitBitd (pCC->base + CONC_dCODECCTL_OFF, 31, 1, DRDY_TIMEOUT))
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return (CODEC_ERR_DATA_TIMEOUT);
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dtemp = pci_inl(pCC->base + CONC_dCODECCTL_OFF);
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if (data)
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*data = (u16_t) dtemp;
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return 0;
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}
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int CODECInit( DEV_STRUCT * pCC )
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{
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int retVal;
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/* All powerdown modes: off */
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retVal = CodecWrite (pCC, AC97_POWERDOWN_CONTROL_STAT, 0x0000U);
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if (OK != retVal)
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return (retVal);
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/* Mute Line Out & set to 0dB attenuation */
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retVal = CodecWrite (pCC, AC97_MASTER_VOLUME, 0x0000U);
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if (OK != retVal)
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return (retVal);
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retVal = CodecWrite (pCC, AC97_MONO_VOLUME, 0x8000U);
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if (OK != retVal)
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return (retVal);
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retVal = CodecWrite (pCC, AC97_PHONE_VOLUME, 0x8008U);
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if (OK != retVal)
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return (retVal);
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retVal = CodecWrite (pCC, AC97_MIC_VOLUME, 0x0008U);
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if (OK != retVal)
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return (retVal);
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retVal = CodecWrite (pCC, AC97_LINE_IN_VOLUME, 0x0808U);
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if (OK != retVal)
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return (retVal);
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retVal = CodecWrite (pCC, AC97_CD_VOLUME, 0x0808U);
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if (OK != retVal)
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return (retVal);
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retVal = CodecWrite (pCC, AC97_AUX_IN_VOLUME, 0x0808U);
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if (OK != retVal)
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return (retVal);
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retVal = CodecWrite (pCC, AC97_PCM_OUT_VOLUME, 0x0808U);
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if (OK != retVal)
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return (retVal);
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retVal = CodecWrite (pCC, AC97_RECORD_GAIN_VOLUME, 0x0000U);
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if (OK != retVal)
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return (retVal);
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/* Connect Line In to ADC */
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retVal = CodecWrite (pCC, AC97_RECORD_SELECT, 0x0404U);
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if (OK != retVal)
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return (retVal);
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retVal = CodecWrite (pCC, AC97_GENERAL_PURPOSE, 0x0000U);
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if (OK != retVal)
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return (retVal);
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return OK;
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}
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