451a6890d6
- Currently the cpu time quantum is timer-ticks based. Thus the remaining quantum is decreased only if the processes is interrupted by a timer tick. As processes block a lot this typically does not happen for normal user processes. Also the quantum depends on the frequency of the timer. - This change makes the quantum miliseconds based. Internally the miliseconds are translated into cpu cycles. Everytime userspace execution is interrupted by kernel the cycles just consumed by the current process are deducted from the remaining quantum. - It makes the quantum system timer frequency independent. - The boot processes quantum is loosely derived from the tick-based quantas and 60Hz timer and subject to future change - the 64bit arithmetics is a little ugly, will be changes once we have compiler support for 64bit integers (soon)
137 lines
2.9 KiB
C
137 lines
2.9 KiB
C
#include "kernel/kernel.h"
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#include "kernel/watchdog.h"
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#include "proto.h"
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#include <minix/minlib.h>
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#include <minix/u64.h>
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#include "apic.h"
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#define CPUID_UNHALTED_CORE_CYCLES_AVAILABLE 0
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#define MSR_PERFMON_CRT0 0xc1
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#define MSR_PERFMON_SEL0 0x186
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#define MSR_PERFMON_SEL0_ENABLE (1 << 22)
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/*
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* Intel architecture performance counters watchdog
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*/
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PRIVATE void intel_arch_watchdog_init(int cpu)
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{
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u64_t cpuf;
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u32_t val;
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ia32_msr_write(MSR_PERFMON_CRT0, 0, 0);
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/* Int, OS, USR, Core ccyles */
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val = 1 << 20 | 1 << 17 | 1 << 16 | 0x3c;
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ia32_msr_write(MSR_PERFMON_SEL0, 0, val);
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/*
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* should give as a tick approx. every 0.5-1s, the perf counter has only
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* lowest 31 bits writable :(
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*/
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cpuf = cpu_get_freq(cpu);
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while (cpuf.hi || cpuf.lo > 0x7fffffffU)
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cpuf = div64u64(cpuf, 2);
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watchdog->resetval = cpuf.lo;
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ia32_msr_write(MSR_PERFMON_CRT0, 0, -cpuf.lo);
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ia32_msr_write(MSR_PERFMON_SEL0, 0, val | MSR_PERFMON_SEL0_ENABLE);
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/* unmask the performance counter interrupt */
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lapic_write(LAPIC_LVTPCR, APIC_ICR_DM_NMI);
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}
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PRIVATE void intel_arch_watchdog_reinit(const int cpu)
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{
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lapic_write(LAPIC_LVTPCR, APIC_ICR_DM_NMI);
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ia32_msr_write(MSR_PERFMON_CRT0, 0, -watchdog->resetval);
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}
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PRIVATE struct arch_watchdog intel_arch_watchdog = {
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/*.init = */ intel_arch_watchdog_init,
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/*.reinit = */ intel_arch_watchdog_reinit
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};
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int arch_watchdog_init(void)
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{
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u32_t eax, ebx, ecx, edx;
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eax = 0xA;
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_cpuid(&eax, &ebx, &ecx, &edx);
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/* FIXME currently we support only watchdog base on the intel
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* architectural performance counters. Some Intel CPUs don't have this
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* feature
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*/
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if (ebx & (1 << CPUID_UNHALTED_CORE_CYCLES_AVAILABLE))
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return -1;
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if (!((((eax >> 8)) & 0xff) > 0))
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return -1;
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watchdog = &intel_arch_watchdog;
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/* Setup PC tas NMI for watchdog, is is masked for now */
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lapic_write(LAPIC_LVTPCR, APIC_ICR_INT_MASK | APIC_ICR_DM_NMI);
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lapic_read(LAPIC_LVTPCR);
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/* double check if LAPIC is enabled */
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if (lapic_addr && watchdog_enabled && watchdog->init) {
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watchdog->init(cpuid);
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}
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return 0;
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}
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void arch_watchdog_lockup(const struct nmi_frame * frame)
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{
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printf("KERNEL LOCK UP\n"
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"eax 0x%08x\n"
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"ecx 0x%08x\n"
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"edx 0x%08x\n"
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"ebx 0x%08x\n"
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"ebp 0x%08x\n"
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"esi 0x%08x\n"
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"edi 0x%08x\n"
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"gs 0x%08x\n"
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"fs 0x%08x\n"
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"es 0x%08x\n"
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"ds 0x%08x\n"
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"pc 0x%08x\n"
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"cs 0x%08x\n"
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"eflags 0x%08x\n",
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frame->eax,
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frame->ecx,
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frame->edx,
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frame->ebx,
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frame->ebp,
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frame->esi,
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frame->edi,
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frame->gs,
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frame->fs,
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frame->es,
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frame->ds,
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frame->pc,
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frame->cs,
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frame->eflags
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);
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panic("Kernel lockup");
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}
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void i386_watchdog_start(void)
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{
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if (watchdog_enabled) {
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if (arch_watchdog_init()) {
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printf("WARNING watchdog initialization "
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"failed! Disabled\n");
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watchdog_enabled = 0;
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}
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else
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BOOT_VERBOSE(printf("Watchdog enabled\n"););
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}
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}
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