1786291e32
- a different set of MSRs and performance counters is used on AMD - when initializing NMI watchdog the test for Intel architecture performance counters feature only applies to Intel now - NMI is enabled if the CPU belongs to a family which has the performance counters that we use
243 lines
5.5 KiB
C
243 lines
5.5 KiB
C
#include "kernel/kernel.h"
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#include "kernel/watchdog.h"
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#include "arch_proto.h"
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#include "glo.h"
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#include <minix/minlib.h>
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#include <minix/u64.h>
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#include "apic.h"
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#define CPUID_UNHALTED_CORE_CYCLES_AVAILABLE 0
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#define INTEL_MSR_PERFMON_CRT0 0xc1
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#define INTEL_MSR_PERFMON_SEL0 0x186
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#define INTEL_MSR_PERFMON_SEL0_ENABLE (1 << 22)
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/*
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* Intel architecture performance counters watchdog
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*/
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PRIVATE struct arch_watchdog intel_arch_watchdog;
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PRIVATE struct arch_watchdog amd_watchdog;
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PRIVATE void intel_arch_watchdog_init(const unsigned cpu)
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{
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u64_t cpuf;
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u32_t val;
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ia32_msr_write(INTEL_MSR_PERFMON_CRT0, 0, 0);
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/* Int, OS, USR, Core ccyles */
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val = 1 << 20 | 1 << 17 | 1 << 16 | 0x3c;
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ia32_msr_write(INTEL_MSR_PERFMON_SEL0, 0, val);
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/*
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* should give as a tick approx. every 0.5-1s, the perf counter has only
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* lowest 31 bits writable :(
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*/
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cpuf = cpu_get_freq(cpu);
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while (cpuf.hi || cpuf.lo > 0x7fffffffU)
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cpuf = div64u64(cpuf, 2);
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cpuf.lo = -cpuf.lo;
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watchdog->resetval = watchdog->watchdog_resetval = cpuf;
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ia32_msr_write(INTEL_MSR_PERFMON_CRT0, 0, cpuf.lo);
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ia32_msr_write(INTEL_MSR_PERFMON_SEL0, 0,
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val | INTEL_MSR_PERFMON_SEL0_ENABLE);
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/* unmask the performance counter interrupt */
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lapic_write(LAPIC_LVTPCR, APIC_ICR_DM_NMI);
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}
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PRIVATE void intel_arch_watchdog_reinit(const unsigned cpu)
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{
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lapic_write(LAPIC_LVTPCR, APIC_ICR_DM_NMI);
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ia32_msr_write(INTEL_MSR_PERFMON_CRT0, 0, watchdog->resetval.lo);
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}
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PUBLIC int arch_watchdog_init(void)
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{
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u32_t eax, ebx, ecx, edx;
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if (!lapic_addr) {
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printf("ERROR : Cannot use NMI watchdog if APIC is not enabled\n");
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return -1;
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}
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if (machine.cpu_type.vendor == CPU_VENDOR_INTEL) {
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eax = 0xA;
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_cpuid(&eax, &ebx, &ecx, &edx);
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/* FIXME currently we support only watchdog based on the intel
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* architectural performance counters. Some Intel CPUs don't have this
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* feature
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*/
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if (ebx & (1 << CPUID_UNHALTED_CORE_CYCLES_AVAILABLE))
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return -1;
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if (!((((eax >> 8)) & 0xff) > 0))
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return -1;
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watchdog = &intel_arch_watchdog;
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} else if (machine.cpu_type.vendor == CPU_VENDOR_AMD) {
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if (machine.cpu_type.family != 6 &&
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machine.cpu_type.family != 15 &&
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machine.cpu_type.family != 16 &&
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machine.cpu_type.family != 17)
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return -1;
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else
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watchdog = &amd_watchdog;
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} else
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return -1;
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/* Setup PC overflow as NMI for watchdog, it is masked for now */
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lapic_write(LAPIC_LVTPCR, APIC_ICR_INT_MASK | APIC_ICR_DM_NMI);
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(void) lapic_read(LAPIC_LVTPCR);
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/* double check if LAPIC is enabled */
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if (lapic_addr && watchdog->init) {
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watchdog->init(cpuid);
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}
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return 0;
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}
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PUBLIC void arch_watchdog_stop(void)
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{
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}
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PUBLIC void arch_watchdog_lockup(const struct nmi_frame * frame)
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{
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printf("KERNEL LOCK UP\n"
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"eax 0x%08x\n"
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"ecx 0x%08x\n"
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"edx 0x%08x\n"
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"ebx 0x%08x\n"
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"ebp 0x%08x\n"
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"esi 0x%08x\n"
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"edi 0x%08x\n"
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"gs 0x%08x\n"
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"fs 0x%08x\n"
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"es 0x%08x\n"
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"ds 0x%08x\n"
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"pc 0x%08x\n"
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"cs 0x%08x\n"
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"eflags 0x%08x\n",
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frame->eax,
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frame->ecx,
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frame->edx,
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frame->ebx,
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frame->ebp,
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frame->esi,
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frame->edi,
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frame->gs,
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frame->fs,
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frame->es,
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frame->ds,
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frame->pc,
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frame->cs,
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frame->eflags
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);
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panic("Kernel lockup");
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}
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PUBLIC int i386_watchdog_start(void)
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{
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if (arch_watchdog_init()) {
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printf("WARNING watchdog initialization "
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"failed! Disabled\n");
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watchdog_enabled = 0;
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return -1;
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}
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else
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BOOT_VERBOSE(printf("Watchdog enabled\n"););
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return 0;
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}
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PRIVATE int intel_arch_watchdog_profile_init(const unsigned freq)
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{
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u64_t cpuf;
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/* FIXME works only if all CPUs have the same freq */
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cpuf = cpu_get_freq(cpuid);
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cpuf = div64u64(cpuf, freq);
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/*
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* if freq is too low and the cpu freq too high we may get in a range of
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* insane value which cannot be handled by the 31bit CPU perf counter
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*/
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if (cpuf.hi != 0 || cpuf.lo > 0x7fffffffU) {
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printf("ERROR : nmi watchdog ticks exceed 31bits, use higher frequency\n");
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return EINVAL;
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}
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cpuf.lo = -cpuf.lo;
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watchdog->profile_resetval = cpuf;
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return OK;
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}
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PRIVATE struct arch_watchdog intel_arch_watchdog = {
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/*.init = */ intel_arch_watchdog_init,
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/*.reinit = */ intel_arch_watchdog_reinit,
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/*.profile_init = */ intel_arch_watchdog_profile_init
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};
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#define AMD_MSR_EVENT_SEL0 0xc0010000
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#define AMD_MSR_EVENT_CTR0 0xc0010004
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#define AMD_MSR_EVENT_SEL0_ENABLE (1 << 22)
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PRIVATE void amd_watchdog_init(const unsigned cpu)
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{
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u64_t cpuf;
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u32_t val;
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ia32_msr_write(AMD_MSR_EVENT_CTR0, 0, 0);
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/* Int, OS, USR, Cycles cpu is running */
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val = 1 << 20 | 1 << 17 | 1 << 16 | 0x76;
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ia32_msr_write(AMD_MSR_EVENT_SEL0, 0, val);
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cpuf = cpu_get_freq(cpu);
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neg64(cpuf);
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watchdog->resetval = watchdog->watchdog_resetval = cpuf;
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ia32_msr_write(AMD_MSR_EVENT_CTR0,
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watchdog->resetval.hi, watchdog->resetval.lo);
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ia32_msr_write(AMD_MSR_EVENT_SEL0, 0,
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val | AMD_MSR_EVENT_SEL0_ENABLE);
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/* unmask the performance counter interrupt */
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lapic_write(LAPIC_LVTPCR, APIC_ICR_DM_NMI);
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}
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PRIVATE void amd_watchdog_reinit(const unsigned cpu)
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{
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lapic_write(LAPIC_LVTPCR, APIC_ICR_DM_NMI);
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ia32_msr_write(AMD_MSR_EVENT_CTR0,
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watchdog->resetval.hi, watchdog->resetval.lo);
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}
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PRIVATE int amd_watchdog_profile_init(const unsigned freq)
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{
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u64_t cpuf;
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/* FIXME works only if all CPUs have the same freq */
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cpuf = cpu_get_freq(cpuid);
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cpuf = div64u64(cpuf, freq);
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neg64(cpuf);
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watchdog->profile_resetval = cpuf;
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return OK;
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}
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PRIVATE struct arch_watchdog amd_watchdog = {
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/*.init = */ amd_watchdog_init,
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/*.reinit = */ amd_watchdog_reinit,
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/*.profile_init = */ amd_watchdog_profile_init
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};
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