b01e9ebfdb
.Split TTY in order to support both x86 and ARM.
.Add support for the TI 16750 UARTs on OMAP35x.
.Various other improvements:
.Kernel messages are printed using generic terminal write
functions. That is, they are no longer directly displayed
on the console.
.The console can now be displayed on any terminal. This
is configured by the "console={tty00,tty01,ttyc2,ttyc3,ttyc4}"
boot variable -- basically any valid /dev/tty* terminal.
.Cutify kernel messages with colors. Configured by
"kernelclr={1,2,3,4,5,6,7}" boot variable.
106 lines
4.2 KiB
C
106 lines
4.2 KiB
C
#ifndef _OMAP_SERIAL_H
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#define _OMAP_SERIAL_H
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/* UART register map */
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#define OMAP3_UART1_BASE 0x4806A000 /* UART1 physical address */
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#define OMAP3_UART2_BASE 0x4806C000 /* UART2 physical address */
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#define OMAP3_UART3_BASE 0x49020000 /* UART3 physical address */
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/* UART registers */
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#define OMAP3_THR 0 /* Transmit holding register */
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#define OMAP3_RHR 0 /* Receive holding register */
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#define OMAP3_DLL 0 /* Divisor latches low */
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#define OMAP3_DLH 1 /* Divisor latches high */
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#define OMAP3_IER 1 /* Interrupt enable register */
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#define OMAP3_IIR 2 /* Interrupt identification register */
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#define OMAP3_EFR 2 /* Extended features register */
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#define OMAP3_FCR 2 /* FIFO control register */
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#define OMAP3_LCR 3 /* Line control register */
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#define OMAP3_MCR 4 /* Modem control register */
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#define OMAP3_LSR 5 /* Line status register */
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#define OMAP3_MSR 6 /* Modem status register */
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#define OMAP3_MDR1 0x08 /* Mode definition register 1 */
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#define OMAP3_MDR2 0x09 /* Mode definition register 2 */
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#define OMAP3_SCR 0x10 /* Supplementary control register */
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#define OMAP3_SSR 0x11 /* Supplementary status register */
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#define OMAP3_SYSC 0x15 /* System configuration register */
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#define OMAP3_SYSS 0x16 /* System status register */
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/* Enhanced Features Register bits */
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#define UART_EFR_ECB 0x10 /* Enhanced control bit */
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/* Interrupt Enable Register bits */
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#define UART_IER_MSI 0x08 /* Modem status interrupt */
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#define UART_IER_RLSI 0x04 /* Receiver line status interrupt */
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#define UART_IER_THRI 0x02 /* Transmitter holding register int. */
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#define UART_IER_RDI 0x01 /* Receiver data interrupt */
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/* FIFO control register */
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#define OMAP_UART_FCR_RX_FIFO_TRIG_SHIFT 6
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#define OMAP_UART_FCR_RX_FIFO_TRIG_MASK (0x3 << 6)
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#define UART_FCR_ENABLE_FIFO 0x01 /* Enable the fifo */
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#define UART_FCR_CLR_RCVR 0x02 /* Clear the RCVR FIFO */
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#define UART_FCR_CLR_XMIT 0x04 /* Clear the XMIT FIFO */
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/* Interrupt Identification Register bits */
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#define UART_IIR_RDI 0x04 /* Data ready interrupt */
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#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
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#define UART_IIR_NO_INT 0x01 /* No interrupt is pending */
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/* Line Control Register bits */
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#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
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#define UART_LCR_SBC 0x40 /* Set break control */
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#define UART_LCR_EPAR 0x10 /* Even parity select */
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#define UART_LCR_PARITY 0x08 /* Enable parity */
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#define UART_LCR_STOP 0x04 /* Stop bits; 0=1 bit, 1=2 bits */
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#define UART_LCR_WLEN5 0x00 /* Wordlength 5 bits */
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#define UART_LCR_WLEN6 0x01 /* Wordlength 6 bits */
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#define UART_LCR_WLEN7 0x02 /* Wordlength 7 bits */
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#define UART_LCR_WLEN8 0x03 /* Wordlength 8 bits */
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#define UART_LCR_CONF_MODE_A UART_LCR_DLAB /* Configuration Mode A */
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#define UART_LCR_CONF_MODE_B 0xBF /* Configuration Mode B */
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/* Line Status Register bits */
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#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
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#define UART_LSR_BI 0x10 /* Break condition */
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#define UART_LSR_DR 0x01 /* Data ready */
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/* Modem Control Register bits */
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#define UART_MCR_TCRTLR 0x40 /* Access TCR/TLR */
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#define UART_MCR_OUT2 0x08 /* Out2 complement */
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#define UART_MCR_RTS 0x02 /* RTS complement */
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#define UART_MCR_DTR 0x01 /* DTR output low */
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/* Mode Definition Register 1 bits */
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#define OMAP_MDR1_DISABLE 0x07
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#define OMAP_MDR1_MODE13X 0x03
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#define OMAP_MDR1_MODE16X 0x00
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/* Modem Status Register bits */
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#define UART_MSR_DCD 0x80 /* Data Carrier Detect */
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#define UART_MSR_CTS 0x10 /* Clear to Send */
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#define UART_MSR_DDCD 0x08 /* Delta DCD */
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/* Supplementary control Register bits */
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#define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7)
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/* System Control Register bits */
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#define UART_SYSC_SOFTRESET 0x02
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/* System Status Register bits */
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#define UART_SYSS_RESETDONE 0x01
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/* Line status register fields */
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#define OMAP3_LSR_TX_FIFO_E (1 << 5) /* Transmit FIFO empty */
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#define OMAP3_LSR_RX_FIFO_E (1 << 0) /* Receive FIFO empty */
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/* Supplementary status register fields */
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#define OMAP3_SSR_TX_FIFO_FULL (1 << 0) /* Transmit FIFO full */
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#define OMAP3_UART3_THR (OMAP3_UART3_BASE + OMAP3_THR)
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#define OMAP3_UART3_IIR (OMAP3_UART3_BASE + OMAP3_IIR)
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#define OMAP3_UART3_LSR (OMAP3_UART3_BASE + OMAP3_LSR)
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#define OMAP3_UART3_SSR (OMAP3_UART3_BASE + OMAP3_SSR)
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#endif /* _OMAP_SERIAL_H */
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