Interrupts where not correctly masked while in kernel, which breaks one of the current main assumptions. Also remove some duplication on ARM asm files, and add a function to check the status of ARM irqs (not compiled by default) Change-Id: I3c25d2b388f93fd8fe423998b94b3c4f140ba831
344 lines
6.5 KiB
C
344 lines
6.5 KiB
C
#ifndef _ARM_CPUFUNC_H
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#define _ARM_CPUFUNC_H
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#if 0
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/* check interrupt state */
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static inline void check_int(unsigned int state, int line)
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{
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unsigned int cpsr = 0;
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asm volatile("mrs %0, cpsr" : "=r" (cpsr));
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if ((cpsr & PSR_F) != (state & PSR_F))
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printf("%d: FIQs are unexpectedly %s\n", line, (cpsr & PSR_F) ? "MASKED" : "UNMASKED");
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if ((cpsr & PSR_I) != (state & PSR_I))
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printf("%d: IRQs are unexpectedly %s\n", line, (cpsr & PSR_I) ? "MASKED" : "UNMASKED");
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}
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#endif
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/* Data memory barrier */
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static inline void dmb(void)
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{
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asm volatile("dmb" : : : "memory");
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}
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/* Data synchronization barrier */
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static inline void dsb(void)
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{
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asm volatile("dsb" : : : "memory");
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}
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/* Instruction synchronization barrier */
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static inline void isb(void)
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{
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asm volatile("isb" : : : "memory");
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}
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static inline void barrier(void)
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{
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dsb();
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isb();
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}
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static inline void refresh_tlb(void)
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{
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dsb();
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/* Invalidate entire unified TLB */
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asm volatile("mcr p15, 0, %[zero], c8, c7, 0 @ TLBIALL\n\t" : : [zero] "r" (0));
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#if 0
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/* Invalidate entire data TLB */
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asm volatile("mcr p15, 0, %[zero], c8, c6, 0" : : [zero] "r" (0));
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/* Invalidate entire instruction TLB */
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asm volatile("mcr p15, 0, %[zero], c8, c5, 0" : : [zero] "r" (0));
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#endif
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#if 0
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/*
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* Invalidate all instruction caches to PoU.
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* Also flushes branch target cache.
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*/
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asm volatile("mcr p15, 0, %[zero], c7, c5, 0" : : [zero] "r" (0));
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/* Invalidate entire branch predictor array */
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asm volatile("mcr p15, 0, %[zero], c7, c5, 6" : : [zero] "r" (0)); /* flush BTB */
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#endif
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dsb();
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isb();
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}
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/* Read System Control Register */
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static inline u32_t read_sctlr()
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{
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u32_t ctl;
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asm volatile("mrc p15, 0, %[ctl], c1, c0, 0 @ Read SCTLR\n\t"
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: [ctl] "=r" (ctl));
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return ctl;
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}
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/* Write System Control Register */
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static inline void write_sctlr(u32_t ctl)
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{
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asm volatile("mcr p15, 0, %[ctl], c1, c0, 0 @ Write SCTLR\n\t"
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: : [ctl] "r" (ctl));
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isb();
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}
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/* Read Translation Table Base Register 0 */
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static inline u32_t read_ttbr0()
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{
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u32_t bar;
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asm volatile("mrc p15, 0, %[bar], c2, c0, 0 @ Read TTBR0\n\t"
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: [bar] "=r" (bar));
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return bar;
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}
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/* Write Translation Table Base Register 0 */
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static inline void write_ttbr0(u32_t bar)
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{
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barrier();
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asm volatile("mcr p15, 0, %[bar], c2, c0, 0 @ Write TTBR0\n\t"
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: : [bar] "r" (bar));
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refresh_tlb();
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}
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/* Reload Translation Table Base Register 0 */
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static inline void reload_ttbr0(void)
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{
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reg_t ttbr = read_ttbr0();
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write_ttbr0(ttbr);
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}
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/* Read Translation Table Base Register 1 */
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static inline u32_t read_ttbr1()
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{
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u32_t bar;
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asm volatile("mrc p15, 0, %[bar], c2, c0, 1 @ Read TTBR1\n\t"
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: [bar] "=r" (bar));
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return bar;
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}
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/* Write Translation Table Base Register 1 */
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static inline void write_ttbr1(u32_t bar)
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{
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barrier();
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asm volatile("mcr p15, 0, %[bar], c2, c0, 1 @ Write TTBR1\n\t"
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: : [bar] "r" (bar));
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refresh_tlb();
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}
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/* Reload Translation Table Base Register 1 */
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static inline void reload_ttbr1(void)
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{
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reg_t ttbr = read_ttbr1();
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write_ttbr1(ttbr);
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}
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/* Read Translation Table Base Control Register */
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static inline u32_t read_ttbcr()
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{
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u32_t bcr;
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asm volatile("mrc p15, 0, %[bcr], c2, c0, 2 @ Read TTBCR\n\t"
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: [bcr] "=r" (bcr));
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return bcr;
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}
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/* Write Translation Table Base Control Register */
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static inline void write_ttbcr(u32_t bcr)
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{
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asm volatile("mcr p15, 0, %[bcr], c2, c0, 2 @ Write TTBCR\n\t"
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: : [bcr] "r" (bcr));
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isb();
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}
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/* Read Domain Access Control Register */
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static inline u32_t read_dacr()
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{
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u32_t dacr;
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asm volatile("mrc p15, 0, %[dacr], c3, c0, 0 @ Read DACR\n\t"
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: [dacr] "=r" (dacr));
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return dacr;
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}
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/* Write Domain Access Control Register */
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static inline void write_dacr(u32_t dacr)
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{
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asm volatile("mcr p15, 0, %[dacr], c3, c0, 0 @ Write DACR\n\t"
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: : [dacr] "r" (dacr));
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isb();
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}
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/* Read Data Fault Status Register */
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static inline u32_t read_dfsr()
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{
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u32_t fsr;
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asm volatile("mrc p15, 0, %[fsr], c5, c0, 0 @ Read DFSR\n\t"
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: [fsr] "=r" (fsr));
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return fsr;
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}
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/* Write Data Fault Status Register */
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static inline void write_dfsr(u32_t fsr)
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{
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asm volatile("mcr p15, 0, %[fsr], c5, c0, 0 @ Write DFSR\n\t"
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: : [fsr] "r" (fsr));
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isb();
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}
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/* Read Instruction Fault Status Register */
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static inline u32_t read_ifsr()
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{
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u32_t fsr;
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asm volatile("mrc p15, 0, %[fsr], c5, c0, 1 @ Read IFSR\n\t"
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: [fsr] "=r" (fsr));
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return fsr;
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}
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/* Write Instruction Fault Status Register */
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static inline void write_ifsr(u32_t fsr)
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{
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asm volatile("mcr p15, 0, %[fsr], c5, c0, 1 @ Write IFSR\n\t"
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: : [fsr] "r" (fsr));
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isb();
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}
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/* Read Data Fault Address Register */
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static inline u32_t read_dfar()
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{
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u32_t far;
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asm volatile("mrc p15, 0, %[far], c6, c0, 0 @ Read DFAR\n\t"
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: [far] "=r" (far));
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return far;
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}
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/* Write Data Fault Address Register */
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static inline void write_dfar(u32_t far)
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{
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asm volatile("mcr p15, 0, %[far], c6, c0, 0 @ Write DFAR\n\t"
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: : [far] "r" (far));
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isb();
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}
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/* Read Instruction Fault Address Register */
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static inline u32_t read_ifar()
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{
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u32_t far;
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asm volatile("mrc p15, 0, %[far], c6, c0, 2 @ Read IFAR\n\t"
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: [far] "=r" (far));
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return far;
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}
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/* Write Instruction Fault Address Register */
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static inline void write_ifar(u32_t far)
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{
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asm volatile("mcr p15, 0, %[far], c6, c0, 2 @ Write IFAR\n\t"
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: : [far] "r" (far));
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isb();
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}
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/* Read Vector Base Address Register */
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static inline u32_t read_vbar()
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{
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u32_t vbar;
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asm volatile("mrc p15, 0, %[vbar], c12, c0, 0 @ Read VBAR\n\t"
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: [vbar] "=r" (vbar));
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return vbar;
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}
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/* Write Vector Base Address Register */
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static inline void write_vbar(u32_t vbar)
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{
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asm volatile("mcr p15, 0, %[vbar], c12, c0, 0 @ Write VBAR\n\t"
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: : [vbar] "r" (vbar));
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isb();
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}
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/* Read the Main ID Register */
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static inline u32_t read_midr()
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{
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u32_t id;
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asm volatile("mrc p15, 0, %[id], c0, c0, 0 @ read MIDR\n\t"
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: [id] "=r" (id));
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return id;
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}
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/* Read Auxiliary Control Register */
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static inline u32_t read_actlr()
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{
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u32_t ctl;
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asm volatile("mrc p15, 0, %[ctl], c1, c0, 1 @ Read ACTLR\n\t"
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: [ctl] "=r" (ctl));
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return ctl;
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}
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/* Write Auxiliary Control Register */
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static inline void write_actlr(u32_t ctl)
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{
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asm volatile("mcr p15, 0, %[ctl], c1, c0, 1 @ Write ACTLR\n\t"
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: : [ctl] "r" (ctl));
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isb();
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}
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/* Read Current Program Status Register */
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static inline u32_t read_cpsr()
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{
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u32_t status;
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asm volatile("mrs %[status], cpsr @ read CPSR"
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: [status] "=r" (status));
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return status;
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}
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/* Write Current Program Status Register */
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static inline void write_cpsr(u32_t status)
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{
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asm volatile("msr cpsr_c, %[status] @ write CPSR"
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: : [status] "r" (status));
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}
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#endif /* _ARM_CPUFUNC_H */
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