1d48c0148e
adjust the smp booting procedure for segmentless operation. changes are mostly due to gdt/idt being dependent on paging, because of the high location, and paging being on much sooner because of that too. also smaller fixes: redefine DESC_SIZE, fix kernel makefile variable name (crosscompiling), some null pointer checks that trap now because of a sparser pagetable, acpi sanity checking
58 lines
1.2 KiB
ArmAsm
58 lines
1.2 KiB
ArmAsm
#include <machine/asm.h>
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#include <machine/vm.h>
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#include "archconst.h"
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.balign 4096
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.text
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.code16
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ENTRY(trampoline)
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cli
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/* %cs has some value and we must use the same for data */
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mov %cs, %ax
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mov %ax, %ds
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/* load gdt and idt prepared by bsp */
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lgdtl _C_LABEL(__ap_gdt) - _C_LABEL(trampoline)
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lidtl _C_LABEL(__ap_idt) - _C_LABEL(trampoline)
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/* switch to protected mode */
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mov %cr0, %eax
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orb $1, %al
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mov %eax, %cr0
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/* set page table feature flags: cr4.PSE on, cr4.PGE off */
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movl %cr4, %eax
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orl $I386_CR4_PSE, %eax /* Turn on PSE */
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andl $~I386_CR4_PGE, %eax /* Turn off PGE */
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movl %eax, %cr4
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/* load boot cr3 and turn PG on so CPU can see all of memory */
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movl _C_LABEL(__ap_pt) - _C_LABEL(trampoline), %eax
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movl %eax, %cr3
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movl %cr0, %ecx
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orl $I386_CR0_PG, %ecx
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movl %ecx, %cr0
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/* turn on cr4.PGE after cr0.PG is on */
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movl %cr4, %eax
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orl $I386_CR4_PGE, %eax
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movl %eax, %cr4
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/* jump into regular highly mapped kernel */
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ljmpl $KERN_CS_SELECTOR, $_C_LABEL(startup_ap_32)
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.balign 4
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LABEL(__ap_id)
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.space 4
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LABEL(__ap_pt)
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.space 4
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LABEL(__ap_gdt)
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.space 8
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LABEL(__ap_idt)
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.space 8
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LABEL(__ap_gdt_tab)
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.space GDT_SIZE*DESC_SIZE
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LABEL(__ap_idt_tab)
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.space IDT_SIZE*DESC_SIZE
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LABEL(__trampoline_end)
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