124 lines
3.7 KiB
ArmAsm
124 lines
3.7 KiB
ArmAsm
/* $NetBSD: atomic_swap.S,v 1.8 2013/11/08 22:42:52 matt Exp $ */
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/*-
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* Copyright (c) 2007,2012 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe and Matt Thomas.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "atomic_op_asm.h"
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/*
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* While SWP{B} is sufficient on its own for pre-ARMv7 CPUs, on MP ARMv7 cores
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* SWP{B} is disabled since it's no longer atomic among multiple CPUs. They
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* will actually raise an UNDEFINED exception.
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*
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* So if we use the LDREX/STREX template, but use a SWP instruction followed
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* by a MOV instruction (using a temporary register), that gives a handler
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* for the SWP UNDEFINED exception enough information to "patch" this instance
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* SWP with correct forms of LDREX/STREX. (note that this would happen even
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* "read-only" pages. If the page gets tossed, we will get another exception
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* and fix yet again).
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*/
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ENTRY_NP(_atomic_swap_32)
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mov ip, r0
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1:
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#ifdef _ARM_ARCH_6
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ldrex r0, [ip]
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cmp r0, r1
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#ifdef __thumb__
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beq 99f
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strex r3, r1, [ip]
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cmp r3, #0
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#else
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strexne r3, r1, [ip]
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cmpne r3, #0
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#endif
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#else
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swp r0, r1, [ip]
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cmp r0, r1
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movnes r3, #0
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cmpne r3, #0
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#endif
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bne 1b
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#ifdef _ARM_ARCH_7
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dmb
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#else
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mcr p15, 0, r3, c7, c10, 5 /* data memory barrier */
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#endif
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99:
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RET
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END(_atomic_swap_32)
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ATOMIC_OP_ALIAS(atomic_swap_32,_atomic_swap_32)
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ATOMIC_OP_ALIAS(atomic_swap_uint,_atomic_swap_32)
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ATOMIC_OP_ALIAS(atomic_swap_ulong,_atomic_swap_32)
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ATOMIC_OP_ALIAS(atomic_swap_ptr,_atomic_swap_32)
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STRONG_ALIAS(__sync_lock_test_and_set_4,_atomic_swap_32)
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STRONG_ALIAS(_atomic_swap_uint,_atomic_swap_32)
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STRONG_ALIAS(_atomic_swap_ulong,_atomic_swap_32)
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STRONG_ALIAS(_atomic_swap_ptr,_atomic_swap_32)
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ENTRY_NP(__sync_lock_release_4)
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mov r1, #0
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strb r1, [r0]
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RET
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END(__sync_lock_release_4)
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ENTRY_NP(_atomic_swap_8)
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mov ip, r0
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1:
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#ifdef _ARM_ARCH_6
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ldrexb r0, [ip]
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strexb r3, r1, [ip]
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#else
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swpb r0, r1, [ip]
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mov r3, #0
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#endif
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cmp r3, #0
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bne 1b
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#ifdef _ARM_ARCH_7
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dmb
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#else
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mcr p15, 0, ip, c7, c10, 5 /* data memory barrier */
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#endif
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RET
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END(_atomic_swap_8)
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ATOMIC_OP_ALIAS(atomic_swap_8,_atomic_swap_8)
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ATOMIC_OP_ALIAS(atomic_swap_char,_atomic_swap_8)
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ATOMIC_OP_ALIAS(atomic_swap_uchar,_atomic_swap_8)
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STRONG_ALIAS(__sync_lock_test_and_set_1,_atomic_swap_8)
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STRONG_ALIAS(_atomic_swap_char,_atomic_swap_8)
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STRONG_ALIAS(_atomic_swap_uchar,_atomic_swap_8)
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ENTRY_NP(__sync_lock_release_1)
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mov r1, #0
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strb r1, [r0]
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RET
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END(__sync_lock_release_1)
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