- kernel maintains a cpu_info array which contains various information about each cpu as filled when each cpu boots - the information contains idetification, features etc.
370 lines
8.1 KiB
C
370 lines
8.1 KiB
C
/* This file contains essentially the MP handling code of the Minix kernel.
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*
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* Changes:
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* Apr 1, 2008 Added SMP support.
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*/
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#define _SMP
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#include "kernel/kernel.h"
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#include "kernel/proc.h"
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#include "arch_proto.h"
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#include "kernel/glo.h"
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#include <unistd.h>
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#include <machine/cmos.h>
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#include <machine/bios.h>
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#include <minix/portio.h>
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#include "kernel/spinlock.h"
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#include "kernel/smp.h"
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#include "apic.h"
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#include "acpi.h"
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#include "glo.h"
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_PROTOTYPE(void trampoline, (void));
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/*
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* arguments for trampoline. We need to pass the logical cpu id, gdt and idt.
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* They have to be in location which is reachable using absolute addressing in
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* 16-bit mode
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*/
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extern volatile u32_t __ap_id;
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extern volatile struct segdesc_s __ap_gdt, __ap_idt;
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extern void * __trampoline_end;
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extern u32_t busclock[CONFIG_MAX_CPUS];
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extern int panicking;
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static int volatile ap_cpu_ready;
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static int volatile cpu_down;
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/* there can be at most 255 local APIC ids, each fits in 8 bits */
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PRIVATE unsigned char apicid2cpuid[255];
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PUBLIC unsigned char cpuid2apicid[CONFIG_MAX_CPUS];
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SPINLOCK_DEFINE(smp_cpu_lock)
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SPINLOCK_DEFINE(dispq_lock)
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FORWARD _PROTOTYPE(void smp_init_vars, (void));
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FORWARD _PROTOTYPE(void smp_reinit_vars, (void));
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/*
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* copies the 16-bit AP trampoline code to the first 1M of memory
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*/
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PRIVATE phys_bytes copy_trampoline(void)
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{
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char * s, *end;
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phys_bytes tramp_base;
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unsigned tramp_size;
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tramp_size = (unsigned) &__trampoline_end - (unsigned)&trampoline;
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s = env_get("memory");
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s = (char *) get_value(params_buffer, "memory");
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if (!s)
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return 0;
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while (*s != 0) {
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phys_bytes base = 0xfffffff;
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unsigned size;
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/* Read fresh base and expect colon as next char. */
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base = strtoul(s, &end, 0x10); /* get number */
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if (end != s && *end == ':')
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s = ++end; /* skip ':' */
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else
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*s=0;
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/* Read fresh size and expect comma or assume end. */
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size = strtoul(s, &end, 0x10); /* get number */
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if (end != s && *end == ',')
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s = ++end; /* skip ',' */
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tramp_base = (base + 0xfff) & ~(0xfff);
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/* the address must be less than 1M */
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if (tramp_base >= (1 << 20))
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continue;
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if (size - (tramp_base - base) < tramp_size)
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continue;
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break;
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}
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phys_copy(vir2phys(trampoline), tramp_base, tramp_size);
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return tramp_base;
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}
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PRIVATE void smp_start_aps(void)
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{
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/*
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* Find an address and align it to a 4k boundary.
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*/
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unsigned cpu;
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u32_t biosresetvector;
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phys_bytes trampoline_base, __ap_id_phys;
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/* TODO hack around the alignment problem */
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phys_copy (0x467, vir2phys(&biosresetvector), sizeof(u32_t));
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/* set the bios shutdown code to 0xA */
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outb(RTC_INDEX, 0xF);
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outb(RTC_IO, 0xA);
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/* prepare gdt and idt for the new cpus */
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__ap_gdt = gdt[GDT_INDEX];
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__ap_idt = gdt[IDT_INDEX];
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if (!(trampoline_base = copy_trampoline())) {
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printf("Copying trampoline code failed, cannot boot SMP\n");
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ncpus = 1;
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}
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__ap_id_phys = trampoline_base +
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(phys_bytes) &__ap_id - (phys_bytes)&trampoline;
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/* setup the warm reset vector */
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phys_copy(vir2phys(&trampoline_base), 0x467, sizeof(u32_t));
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/* okay, we're ready to go. boot all of the ap's now. we loop through
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* using the processor's apic id values.
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*/
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for (cpu = 0; cpu < ncpus; cpu++) {
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ap_cpu_ready = -1;
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/* Don't send INIT/SIPI to boot cpu. */
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if((apicid() == cpuid2apicid[cpu]) &&
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(apicid() == bsp_lapic_id)) {
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continue;
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}
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__ap_id = cpu;
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phys_copy(vir2phys(__ap_id), __ap_id_phys, sizeof(__ap_id));
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mfence();
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if (apic_send_init_ipi(cpu, trampoline_base) ||
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apic_send_startup_ipi(cpu, trampoline_base)) {
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printf("WARNING cannot boot cpu %d\n", cpu);
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continue;
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}
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/* wait for 5 secs for the processors to boot */
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lapic_set_timer_one_shot(5000000);
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while (lapic_read(LAPIC_TIMER_CCR)) {
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if (ap_cpu_ready == cpu) {
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cpu_set_flag(cpu, CPU_IS_READY);
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break;
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}
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}
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if (ap_cpu_ready == -1) {
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printf("WARNING : CPU %d didn't boot\n", cpu);
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}
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}
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phys_copy(vir2phys(&biosresetvector),(phys_bytes)0x467,sizeof(u32_t));
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outb(RTC_INDEX, 0xF);
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outb(RTC_IO, 0);
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bsp_finish_booting();
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NOT_REACHABLE;
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}
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PUBLIC void smp_halt_cpu (void)
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{
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NOT_IMPLEMENTED;
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}
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PUBLIC void smp_shutdown_aps(void)
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{
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unsigned cpu;
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unsigned aid = apicid();
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unsigned local_cpu = cpuid;
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if (ncpus == 1)
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goto exit_shutdown_aps;
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/* we must let the other cpus enter the kernel mode */
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BKL_UNLOCK();
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for (cpu = 0; cpu < ncpus; cpu++) {
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if (cpu == cpuid)
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continue;
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if (!cpu_test_flag(cpu, CPU_IS_READY)) {
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printf("CPU %d didn't boot\n", cpu);
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continue;
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}
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cpu_down = -1;
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barrier();
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apic_send_ipi(APIC_SMP_CPU_HALT_VECTOR, cpu, APIC_IPI_DEST);
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/* wait for the cpu to be down */
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while (cpu_down != cpu);
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printf("CPU %d is down\n", cpu);
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cpu_clear_flag(cpu, CPU_IS_READY);
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}
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exit_shutdown_aps:
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ioapic_disable_all();
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lapic_disable();
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ncpus = 1; /* hopefully !!! */
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lapic_addr = lapic_eoi_addr = 0;
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return;
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}
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PRIVATE void ap_finish_booting(void)
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{
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unsigned cpu = cpuid;
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/* inform the world of our presence. */
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ap_cpu_ready = cpu;
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while(!i386_paging_enabled)
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arch_pause();
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/*
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* Finish processor initialisation. CPUs must be excluded from running.
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* lapic timer calibration locks and unlocks the BKL because of the
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* nested interrupts used for calibration. Therefore BKL is not good
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* enough, the boot_lock must be held.
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*/
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spinlock_lock(&boot_lock);
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BKL_LOCK();
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/*
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* we must load some page tables befre we turn paging on. As VM is
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* always present we use those
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*/
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segmentation2paging(proc_addr(VM_PROC_NR));
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printf("CPU %d paging is on\n", cpu);
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cpu_identify();
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lapic_enable(cpu);
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fpu_init();
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if (app_cpu_init_timer(system_hz)) {
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panic("FATAL : failed to initialize timer interrupts CPU %d, "
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"cannot continue without any clock source!", cpu);
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}
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/* FIXME assign CPU local idle structure */
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get_cpulocal_var(proc_ptr) = get_cpulocal_var_ptr(idle_proc);
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get_cpulocal_var(bill_ptr) = get_cpulocal_var_ptr(idle_proc);
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ap_boot_finished(cpu);
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spinlock_unlock(&boot_lock);
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switch_to_user();
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NOT_REACHABLE;
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}
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PUBLIC void smp_ap_boot(void)
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{
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switch_k_stack((char *)get_k_stack_top(__ap_id) -
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X86_STACK_TOP_RESERVED, ap_finish_booting);
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}
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PRIVATE void smp_reinit_vars(void)
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{
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int i;
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lapic_addr = lapic_eoi_addr = 0;
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ioapic_enabled = 0;
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ncpus = 1;
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}
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PRIVATE void tss_init_all(void)
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{
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unsigned cpu;
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for(cpu = 0; cpu < ncpus ; cpu++)
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tss_init(cpu, get_k_stack_top(cpu));
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}
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PRIVATE int discover_cpus(void)
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{
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struct acpi_madt_lapic * cpu;
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while (ncpus < CONFIG_MAX_CPUS && (cpu = acpi_get_lapic_next())) {
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apicid2cpuid[cpu->apic_id] = ncpus;
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cpuid2apicid[ncpus] = cpu->apic_id;
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printf("CPU %3d local APIC id %3d\n", ncpus, cpu->apic_id);
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ncpus++;
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}
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return ncpus;
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}
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PUBLIC void smp_init (void)
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{
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/* read the MP configuration */
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if (!discover_cpus()) {
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ncpus = 1;
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goto uniproc_fallback;
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}
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lapic_addr = phys2vir(LOCAL_APIC_DEF_ADDR);
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ioapic_enabled = 0;
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tss_init_all();
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/*
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* we still run on the boot stack and we cannot use cpuid as its value
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* wasn't set yet. apicid2cpuid initialized in mps_init()
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*/
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bsp_cpu_id = apicid2cpuid[apicid()];
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if (!lapic_enable(bsp_cpu_id)) {
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printf("ERROR : failed to initialize BSP Local APIC\n");
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goto uniproc_fallback;
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}
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bsp_lapic_id = apicid();
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acpi_init();
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if (!detect_ioapics()) {
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lapic_disable();
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lapic_addr = 0x0;
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goto uniproc_fallback;
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}
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ioapic_enable_all();
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if (ioapic_enabled)
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machine.apic_enabled = 1;
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/* set smp idt entries. */
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apic_idt_init(0); /* Not a reset ! */
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idt_reload();
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BOOT_VERBOSE(printf("SMP initialized\n"));
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switch_k_stack((char *)get_k_stack_top(bsp_cpu_id) -
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X86_STACK_TOP_RESERVED, smp_start_aps);
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return;
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uniproc_fallback:
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apic_idt_init(1); /* Reset to PIC idt ! */
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idt_reload();
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smp_reinit_vars (); /* revert to a single proc system. */
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intr_init (INTS_MINIX, 0); /* no auto eoi */
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printf("WARNING : SMP initialization failed\n");
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}
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PUBLIC void arch_smp_halt_cpu(void)
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{
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/* say that we are down */
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cpu_down = cpuid;
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barrier();
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/* unlock the BKL and don't continue */
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BKL_UNLOCK();
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for(;;);
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}
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PUBLIC void arch_send_smp_schedule_ipi(unsigned cpu)
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{
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apic_send_ipi(APIC_SMP_SCHED_PROC_VECTOR, cpu, APIC_IPI_DEST);
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}
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