104 lines
5.2 KiB
C
104 lines
5.2 KiB
C
/* $NetBSD: vfpreg.h,v 1.6 2012/09/22 19:45:53 matt Exp $ */
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/*
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* Copyright (c) 2008 ARM Ltd
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the company may not be used to endorse or promote
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* products derived from this software without specific prior written
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* permission.
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*
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* THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
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* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _VFPREG_H
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#define _VFPREG_H
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/* FPSID regsiter */
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#define VFP_FPSID_IMP_MSK 0xff000000 /* Implementer */
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#define VFP_FPSID_IMP_ARM 0x41000000 /* Implementer: ARM */
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#define VFP_FPSID_SW 0x00800000 /* VFP implemented in SW */
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#define VFP_FPSID_FMT_MSK 0x00600000 /* FLDMX/FSTMX Format */
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#define VFP_FPSID_FMT_1 0x00000000 /* Standard format 1 */
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#define VFP_FPSID_FMT_2 0x00200000 /* Standard format 2 */
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#define VFP_FPSID_FMT_WEIRD 0x00600000 /* Non-standard format */
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#define VFP_FPSID_SP 0x00100000 /* Only single precision */
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#define VFP_FPSID_ARCH_MSK 0x000f0000 /* Architecture */
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#define VFP_FPSID_ARCH_V1 0x00000000 /* Arch VFPv1 */
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#define VFP_FPSID_ARCH_V2 0x00010000 /* Arch VFPv2 */
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#define VFP_FPSID_ARCH_V3_2 0x00020000 /* Arch VFPv3 (subarch v2) */
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#define VFP_FPSID_ARCH_V3 0x00030000 /* Arch VFPv3 (no subarch) */
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#define VFP_FPSID_ARCH_V3_3 0x00040000 /* Arch VFPv3 (subarch v3) */
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#define VFP_FPSID_PART_MSK 0x0000ff00 /* Part number */
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#define VFP_FPSID_PART_VFP10 0x00001000 /* VFP10 */
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#define VFP_FPSID_PART_VFP11 0x00002000 /* VFP11 */
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#define VFP_FPSID_PART_VFP30 0x00003000 /* VFP30 */
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#define VFP_FPSID_VAR_MSK 0x000000f0 /* Variant */
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#define VFP_FPSID_VAR_ARM10 0x000000a0 /* Variant ARM10 */
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#define VFP_FPSID_VAR_ARM11 0x000000b0 /* Variant ARM11 */
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#define VFP_FPSID_REV_MSK 0x0000000f /* Revision */
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#define FPU_VFP10_ARM10E 0x410001a0 /* Really a VFPv2 part */
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#define FPU_VFP11_ARM11 0x410120b0
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#define FPU_VFP_CORTEXA5 0x41023050
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#define FPU_VFP_CORTEXA7 0x41023070
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#define FPU_VFP_CORTEXA8 0x410330c0
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#define FPU_VFP_CORTEXA9 0x41033090
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#define VFP_FPEXC_EX 0x80000000 /* Exception status bit */
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#define VFP_FPEXC_EN 0x40000000 /* VFP Enable bit */
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#define VFP_FPEXC_FP2V 0x10000000 /* FPINST2 instruction valid */
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#define VFP_FPEXC_VECITR 0x00000700 /* Vector iteration count */
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#define VFP_FPEXC_INV 0x00000080 /* Input exception flag */
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#define VFP_FPEXC_UFC 0x00000080 /* Potential underflow flag */
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#define VFP_FPEXC_OFC 0x00000080 /* Potential overflow flag */
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#define VFP_FPEXC_IOC 0x00000080 /* Potential inv. op. flag */
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#define VFP_FPSCR_N 0x80000000 /* set if compare <= result */
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#define VFP_FPSCR_Z 0x40000000 /* set if compare = result */
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#define VFP_FPSCR_C 0x20000000 /* set if compare (=,>=,UNORD) result */
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#define VFP_FPSCR_V 0x10000000 /* set if compare UNORD result */
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#define VFP_FPSCR_DN 0x02000000 /* Default NaN mode */
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#define VFP_FPSCR_FZ 0x01000000 /* Flush-to-zero mode */
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#define VFP_FPSCR_RMODE 0x00c00000 /* Rounding Mode */
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#define VFP_FPSCR_RZ 0x00c00000 /* round towards zero (RZ) */
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#define VFP_FPSCR_RM 0x00800000 /* round towards +INF (RP) */
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#define VFP_FPSCR_RP 0x00400000 /* round towards -INF (RM) */
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#define VFP_FPSCR_RN 0x00000000 /* round to nearest (RN) */
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#define VFP_FPSCR_STRIDE 0x00300000 /* Vector Stride */
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#define VFP_FPSCR_LEN 0x00070000 /* Vector Length */
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#define VFP_FPSCR_IDE 0x00008000 /* Inout Subnormal Exception Enable */
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#define VFP_FPSCR_ESUM 0x00001f00 /* IXE|UFE|OFE|DZE|IOE */
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#define VFP_FPSCR_IXE 0x00001000 /* Inexact Exception Enable */
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#define VFP_FPSCR_UFE 0x00000800 /* Underflow Exception Enable */
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#define VFP_FPSCR_OFE 0x00000400 /* Overflow Exception Enable */
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#define VFP_FPSCR_DZE 0x00000200 /* Inexact Exception Enable */
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#define VFP_FPSCR_IOE 0x00000100 /* Invalid Operation Cumulative Flag */
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#define VFP_FPSCR_IDC 0x00000080 /* Input Subnormal Cumlative Flag */
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#define VFP_FPSCR_CSUM 0x0000001f /* IXC|UFC|OFC|DZC|IOC */
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#define VFP_FPSCR_IXC 0x00000010 /* Inexact Cumulative Flag */
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#define VFP_FPSCR_UFC 0x00000008 /* Underflow Cumulative Flag */
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#define VFP_FPSCR_OFC 0x00000004 /* Overflow Cumulative Flag */
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#define VFP_FPSCR_DZC 0x00000002 /* DivByZero Cumulative Flag */
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#define VFP_FPSCR_IOC 0x00000001 /* Invalid Operation Cumulative Flag */
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#endif /* _VFPREG_H */
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