197 lines
5.5 KiB
C
197 lines
5.5 KiB
C
/* $NetBSD: lock.h,v 1.21 2012/08/31 17:29:08 matt Exp $ */
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/*-
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* Copyright (c) 2000, 2001 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Machine-dependent spin lock operations.
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*
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* NOTE: The SWP insn used here is available only on ARM architecture
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* version 3 and later (as well as 2a). What we are going to do is
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* expect that the kernel will trap and emulate the insn. That will
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* be slow, but give us the atomicity that we need.
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*/
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#ifndef _ARM_LOCK_H_
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#define _ARM_LOCK_H_
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static __inline int
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__SIMPLELOCK_LOCKED_P(__cpu_simple_lock_t *__ptr)
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{
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return *__ptr == __SIMPLELOCK_LOCKED;
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}
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static __inline int
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__SIMPLELOCK_UNLOCKED_P(__cpu_simple_lock_t *__ptr)
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{
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return *__ptr == __SIMPLELOCK_UNLOCKED;
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}
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static __inline void
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__cpu_simple_lock_clear(__cpu_simple_lock_t *__ptr)
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{
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*__ptr = __SIMPLELOCK_UNLOCKED;
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}
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static __inline void
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__cpu_simple_lock_set(__cpu_simple_lock_t *__ptr)
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{
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*__ptr = __SIMPLELOCK_LOCKED;
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}
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#ifdef _KERNEL
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#include <arm/cpufunc.h>
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#define mb_read drain_writebuf /* in cpufunc.h */
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#define mb_write drain_writebuf /* in cpufunc.h */
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#define mb_memory drain_writebuf /* in cpufunc.h */
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#endif
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#if defined(_KERNEL)
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static __inline __cpu_simple_lock_t
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__swp(__cpu_simple_lock_t __val, volatile __cpu_simple_lock_t *__ptr)
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{
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#ifdef _ARM_ARCH_6
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__cpu_simple_lock_t __rv, __tmp;
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if (sizeof(*__ptr) == 1) {
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__asm volatile(
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"1:\t"
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"ldrexb\t%[__rv], [%[__ptr]]" "\n\t"
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"cmp\t%[__rv],%[__val]" "\n\t"
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"strexbne\t%[__tmp], %[__val], [%[__ptr]]" "\n\t"
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"cmpne\t%[__tmp], #0" "\n\t"
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"bne\t1b" "\n\t"
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#ifdef _ARM_ARCH_7
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"dmb"
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#else
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"mcr\tp15, 0, %[__tmp], c7, c10, 5"
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#endif
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: [__rv] "=&r" (__rv), [__tmp] "=&r"(__tmp)
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: [__val] "r" (__val), [__ptr] "r" (__ptr) : "cc", "memory");
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} else {
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__asm volatile(
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"1:\t"
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"ldrex\t%[__rv], [%[__ptr]]" "\n\t"
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"cmp\t%[__rv],%[__val]" "\n\t"
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"strexne\t%[__tmp], %[__val], [%[__ptr]]" "\n\t"
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"cmpne\t%[__tmp], #0" "\n\t"
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"bne\t1b" "\n\t"
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#ifdef _ARM_ARCH_7
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"nop"
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#else
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"mcr\tp15, 0, %[__tmp], c7, c10, 5"
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#endif
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: [__rv] "=&r" (__rv), [__tmp] "=&r"(__tmp)
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: [__val] "r" (__val), [__ptr] "r" (__ptr) : "cc", "memory");
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}
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return __rv;
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#else
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__asm volatile("swpb %0, %1, [%2]"
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: "=&r" (__val) : "r" (__val), "r" (__ptr) : "memory");
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return __val;
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#endif
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}
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#else
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/*
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* On Cortex-A9 (SMP), SWP no longer guarantees atomic results. Thus we pad
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* out SWP so that when the A9 generates an undefined exception we can replace
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* the SWP/MOV instructions with the right LDREX/STREX instructions.
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*
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* This is why we force the SWP into the template needed for LDREX/STREX
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* including the extra instructions and extra register for testing the result.
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*/
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static __inline int
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__swp(int __val, volatile int *__ptr)
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{
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int __rv, __tmp;
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__asm volatile(
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"1:\t"
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#ifdef _ARM_ARCH_6
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"ldrex\t%[__rv], [%[__ptr]]" "\n\t"
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"cmp\t%[__rv],%[__val]" "\n\t"
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"strexne\t%[__tmp], %[__val], [%[__ptr]]" "\n\t"
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#else
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"swp\t%[__rv], %[__val], [%[__ptr]]" "\n\t"
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"cmp\t%[__rv],%[__val]" "\n\t"
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"movs\t%[__tmp], #0" "\n\t"
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#endif
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"cmpne\t%[__tmp], #0" "\n\t"
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"bne\t1b" "\n\t"
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#ifdef _ARM_ARCH_7
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"dmb"
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#elif defined(_ARM_ARCH_6)
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"mcr\tp15, 0, %[__tmp], c7, c10, 5"
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#else
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"nop"
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#endif
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: [__rv] "=&r" (__rv), [__tmp] "=&r"(__tmp)
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: [__val] "r" (__val), [__ptr] "r" (__ptr) : "cc", "memory");
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return __rv;
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}
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#endif /* _KERNEL */
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static __inline void __attribute__((__unused__))
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__cpu_simple_lock_init(__cpu_simple_lock_t *alp)
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{
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*alp = __SIMPLELOCK_UNLOCKED;
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#ifdef _ARM_ARCH_7
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__asm __volatile("dsb");
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#endif
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}
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static __inline void __attribute__((__unused__))
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__cpu_simple_lock(__cpu_simple_lock_t *alp)
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{
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while (__swp(__SIMPLELOCK_LOCKED, alp) != __SIMPLELOCK_UNLOCKED)
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continue;
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}
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static __inline int __attribute__((__unused__))
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__cpu_simple_lock_try(__cpu_simple_lock_t *alp)
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{
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return (__swp(__SIMPLELOCK_LOCKED, alp) == __SIMPLELOCK_UNLOCKED);
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}
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static __inline void __attribute__((__unused__))
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__cpu_simple_unlock(__cpu_simple_lock_t *alp)
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{
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#ifdef _ARM_ARCH_7
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__asm __volatile("dmb");
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#endif
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*alp = __SIMPLELOCK_UNLOCKED;
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#ifdef _ARM_ARCH_7
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__asm __volatile("dsb");
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#endif
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}
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#endif /* _ARM_LOCK_H_ */
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