493 lines
17 KiB
C
493 lines
17 KiB
C
/* $NetBSD: bus_defs.h,v 1.2 2012/09/18 05:47:27 matt Exp $ */
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/*-
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* Copyright (c) 1996, 1997, 1998, 2001 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
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* NASA Ames Research Center.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Copyright (c) 1996 Charles M. Hannum. All rights reserved.
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* Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Christopher G. Demetriou
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* for the NetBSD Project.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _ARM32_BUS_DEFS_H_
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#define _ARM32_BUS_DEFS_H_
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#if defined(_KERNEL_OPT)
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#include "opt_arm_bus_space.h"
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#endif
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/*
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* Addresses (in bus space).
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*/
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typedef u_long bus_addr_t;
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typedef u_long bus_size_t;
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/*
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* Access methods for bus space.
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*/
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typedef struct bus_space *bus_space_tag_t;
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typedef u_long bus_space_handle_t;
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/*
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* int bus_space_map(bus_space_tag_t t, bus_addr_t addr,
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* bus_size_t size, int flags, bus_space_handle_t *bshp);
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*
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* Map a region of bus space.
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*/
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#define BUS_SPACE_MAP_CACHEABLE 0x01
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#define BUS_SPACE_MAP_LINEAR 0x02
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#define BUS_SPACE_MAP_PREFETCHABLE 0x04
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struct bus_space {
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/* cookie */
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void *bs_cookie;
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/* mapping/unmapping */
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int (*bs_map)(void *, bus_addr_t, bus_size_t,
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int, bus_space_handle_t *);
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void (*bs_unmap)(void *, bus_space_handle_t,
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bus_size_t);
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int (*bs_subregion)(void *, bus_space_handle_t,
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bus_size_t, bus_size_t, bus_space_handle_t *);
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/* allocation/deallocation */
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int (*bs_alloc)(void *, bus_addr_t, bus_addr_t,
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bus_size_t, bus_size_t, bus_size_t, int,
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bus_addr_t *, bus_space_handle_t *);
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void (*bs_free)(void *, bus_space_handle_t,
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bus_size_t);
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/* get kernel virtual address */
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void * (*bs_vaddr)(void *, bus_space_handle_t);
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/* mmap bus space for user */
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paddr_t (*bs_mmap)(void *, bus_addr_t, off_t, int, int);
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/* barrier */
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void (*bs_barrier)(void *, bus_space_handle_t,
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bus_size_t, bus_size_t, int);
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/* read (single) */
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u_int8_t (*bs_r_1)(void *, bus_space_handle_t,
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bus_size_t);
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u_int16_t (*bs_r_2)(void *, bus_space_handle_t,
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bus_size_t);
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u_int32_t (*bs_r_4)(void *, bus_space_handle_t,
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bus_size_t);
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u_int64_t (*bs_r_8)(void *, bus_space_handle_t,
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bus_size_t);
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/* read multiple */
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void (*bs_rm_1)(void *, bus_space_handle_t,
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bus_size_t, u_int8_t *, bus_size_t);
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void (*bs_rm_2)(void *, bus_space_handle_t,
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bus_size_t, u_int16_t *, bus_size_t);
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void (*bs_rm_4)(void *, bus_space_handle_t,
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bus_size_t, u_int32_t *, bus_size_t);
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void (*bs_rm_8)(void *, bus_space_handle_t,
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bus_size_t, u_int64_t *, bus_size_t);
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/* read region */
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void (*bs_rr_1)(void *, bus_space_handle_t,
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bus_size_t, u_int8_t *, bus_size_t);
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void (*bs_rr_2)(void *, bus_space_handle_t,
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bus_size_t, u_int16_t *, bus_size_t);
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void (*bs_rr_4)(void *, bus_space_handle_t,
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bus_size_t, u_int32_t *, bus_size_t);
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void (*bs_rr_8)(void *, bus_space_handle_t,
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bus_size_t, u_int64_t *, bus_size_t);
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/* write (single) */
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void (*bs_w_1)(void *, bus_space_handle_t,
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bus_size_t, u_int8_t);
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void (*bs_w_2)(void *, bus_space_handle_t,
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bus_size_t, u_int16_t);
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void (*bs_w_4)(void *, bus_space_handle_t,
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bus_size_t, u_int32_t);
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void (*bs_w_8)(void *, bus_space_handle_t,
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bus_size_t, u_int64_t);
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/* write multiple */
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void (*bs_wm_1)(void *, bus_space_handle_t,
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bus_size_t, const u_int8_t *, bus_size_t);
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void (*bs_wm_2)(void *, bus_space_handle_t,
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bus_size_t, const u_int16_t *, bus_size_t);
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void (*bs_wm_4)(void *, bus_space_handle_t,
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bus_size_t, const u_int32_t *, bus_size_t);
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void (*bs_wm_8)(void *, bus_space_handle_t,
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bus_size_t, const u_int64_t *, bus_size_t);
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/* write region */
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void (*bs_wr_1)(void *, bus_space_handle_t,
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bus_size_t, const u_int8_t *, bus_size_t);
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void (*bs_wr_2)(void *, bus_space_handle_t,
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bus_size_t, const u_int16_t *, bus_size_t);
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void (*bs_wr_4)(void *, bus_space_handle_t,
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bus_size_t, const u_int32_t *, bus_size_t);
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void (*bs_wr_8)(void *, bus_space_handle_t,
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bus_size_t, const u_int64_t *, bus_size_t);
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/* set multiple */
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void (*bs_sm_1)(void *, bus_space_handle_t,
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bus_size_t, u_int8_t, bus_size_t);
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void (*bs_sm_2)(void *, bus_space_handle_t,
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bus_size_t, u_int16_t, bus_size_t);
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void (*bs_sm_4)(void *, bus_space_handle_t,
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bus_size_t, u_int32_t, bus_size_t);
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void (*bs_sm_8)(void *, bus_space_handle_t,
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bus_size_t, u_int64_t, bus_size_t);
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/* set region */
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void (*bs_sr_1)(void *, bus_space_handle_t,
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bus_size_t, u_int8_t, bus_size_t);
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void (*bs_sr_2)(void *, bus_space_handle_t,
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bus_size_t, u_int16_t, bus_size_t);
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void (*bs_sr_4)(void *, bus_space_handle_t,
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bus_size_t, u_int32_t, bus_size_t);
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void (*bs_sr_8)(void *, bus_space_handle_t,
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bus_size_t, u_int64_t, bus_size_t);
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/* copy */
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void (*bs_c_1)(void *, bus_space_handle_t, bus_size_t,
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bus_space_handle_t, bus_size_t, bus_size_t);
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void (*bs_c_2)(void *, bus_space_handle_t, bus_size_t,
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bus_space_handle_t, bus_size_t, bus_size_t);
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void (*bs_c_4)(void *, bus_space_handle_t, bus_size_t,
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bus_space_handle_t, bus_size_t, bus_size_t);
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void (*bs_c_8)(void *, bus_space_handle_t, bus_size_t,
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bus_space_handle_t, bus_size_t, bus_size_t);
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#ifdef __BUS_SPACE_HAS_STREAM_METHODS
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/* read stream (single) */
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u_int8_t (*bs_r_1_s)(void *, bus_space_handle_t,
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bus_size_t);
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u_int16_t (*bs_r_2_s)(void *, bus_space_handle_t,
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bus_size_t);
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u_int32_t (*bs_r_4_s)(void *, bus_space_handle_t,
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bus_size_t);
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u_int64_t (*bs_r_8_s)(void *, bus_space_handle_t,
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bus_size_t);
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/* read multiple stream */
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void (*bs_rm_1_s)(void *, bus_space_handle_t,
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bus_size_t, u_int8_t *, bus_size_t);
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void (*bs_rm_2_s)(void *, bus_space_handle_t,
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bus_size_t, u_int16_t *, bus_size_t);
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void (*bs_rm_4_s)(void *, bus_space_handle_t,
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bus_size_t, u_int32_t *, bus_size_t);
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void (*bs_rm_8_s)(void *, bus_space_handle_t,
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bus_size_t, u_int64_t *, bus_size_t);
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/* read region stream */
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void (*bs_rr_1_s)(void *, bus_space_handle_t,
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bus_size_t, u_int8_t *, bus_size_t);
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void (*bs_rr_2_s)(void *, bus_space_handle_t,
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bus_size_t, u_int16_t *, bus_size_t);
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void (*bs_rr_4_s)(void *, bus_space_handle_t,
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bus_size_t, u_int32_t *, bus_size_t);
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void (*bs_rr_8_s)(void *, bus_space_handle_t,
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bus_size_t, u_int64_t *, bus_size_t);
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/* write stream (single) */
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void (*bs_w_1_s)(void *, bus_space_handle_t,
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bus_size_t, u_int8_t);
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void (*bs_w_2_s)(void *, bus_space_handle_t,
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bus_size_t, u_int16_t);
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void (*bs_w_4_s)(void *, bus_space_handle_t,
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bus_size_t, u_int32_t);
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void (*bs_w_8_s)(void *, bus_space_handle_t,
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bus_size_t, u_int64_t);
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/* write multiple stream */
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void (*bs_wm_1_s)(void *, bus_space_handle_t,
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bus_size_t, const u_int8_t *, bus_size_t);
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void (*bs_wm_2_s)(void *, bus_space_handle_t,
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bus_size_t, const u_int16_t *, bus_size_t);
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void (*bs_wm_4_s)(void *, bus_space_handle_t,
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bus_size_t, const u_int32_t *, bus_size_t);
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void (*bs_wm_8_s)(void *, bus_space_handle_t,
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bus_size_t, const u_int64_t *, bus_size_t);
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/* write region stream */
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void (*bs_wr_1_s)(void *, bus_space_handle_t,
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bus_size_t, const u_int8_t *, bus_size_t);
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void (*bs_wr_2_s)(void *, bus_space_handle_t,
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bus_size_t, const u_int16_t *, bus_size_t);
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void (*bs_wr_4_s)(void *, bus_space_handle_t,
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bus_size_t, const u_int32_t *, bus_size_t);
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void (*bs_wr_8_s)(void *, bus_space_handle_t,
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bus_size_t, const u_int64_t *, bus_size_t);
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#endif /* __BUS_SPACE_HAS_STREAM_METHODS */
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};
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#define BUS_SPACE_BARRIER_READ 0x01
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#define BUS_SPACE_BARRIER_WRITE 0x02
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#define BUS_SPACE_ALIGNED_POINTER(p, t) ALIGNED_POINTER(p, t)
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/* Bus Space DMA macros */
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/*
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* Flags used in various bus DMA methods.
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*/
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#define BUS_DMA_WAITOK 0x000 /* safe to sleep (pseudo-flag) */
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#define BUS_DMA_NOWAIT 0x001 /* not safe to sleep */
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#define BUS_DMA_ALLOCNOW 0x002 /* perform resource allocation now */
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#define BUS_DMA_COHERENT 0x004 /* hint: map memory DMA coherent */
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#define BUS_DMA_STREAMING 0x008 /* hint: sequential, unidirectional */
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#define BUS_DMA_BUS1 0x010 /* placeholders for bus functions... */
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#define BUS_DMA_BUS2 0x020
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#define BUS_DMA_BUS3 0x040
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#define BUS_DMA_BUS4 0x080
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#define BUS_DMA_READ 0x100 /* mapping is device -> memory only */
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#define BUS_DMA_WRITE 0x200 /* mapping is memory -> device only */
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#define BUS_DMA_NOCACHE 0x400 /* hint: map non-cached memory */
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/*
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* Private flags stored in the DMA map.
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*/
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#define _BUS_DMAMAP_COHERENT 0x10000 /* no cache flush necessary on sync */
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/* Forwards needed by prototypes below. */
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struct mbuf;
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struct uio;
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/*
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* Operations performed by bus_dmamap_sync().
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*/
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#define BUS_DMASYNC_PREREAD 0x01 /* pre-read synchronization */
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#define BUS_DMASYNC_POSTREAD 0x02 /* post-read synchronization */
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#define BUS_DMASYNC_PREWRITE 0x04 /* pre-write synchronization */
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#define BUS_DMASYNC_POSTWRITE 0x08 /* post-write synchronization */
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typedef struct arm32_bus_dma_tag *bus_dma_tag_t;
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typedef struct arm32_bus_dmamap *bus_dmamap_t;
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#define BUS_DMA_TAG_VALID(t) ((t) != (bus_dma_tag_t)0)
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/*
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* bus_dma_segment_t
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*
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* Describes a single contiguous DMA transaction. Values
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* are suitable for programming into DMA registers.
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*/
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struct arm32_bus_dma_segment {
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/*
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* PUBLIC MEMBERS: these are used by machine-independent code.
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*/
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bus_addr_t ds_addr; /* DMA address */
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bus_size_t ds_len; /* length of transfer */
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};
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typedef struct arm32_bus_dma_segment bus_dma_segment_t;
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/*
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* arm32_dma_range
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*
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* This structure describes a valid DMA range.
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*/
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struct arm32_dma_range {
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bus_addr_t dr_sysbase; /* system base address */
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bus_addr_t dr_busbase; /* appears here on bus */
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bus_size_t dr_len; /* length of range */
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};
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/*
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* bus_dma_tag_t
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*
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* A machine-dependent opaque type describing the implementation of
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* DMA for a given bus.
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*/
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struct arm32_bus_dma_tag {
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/*
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* DMA range for this tag. If the page doesn't fall within
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* one of these ranges, an error is returned. The caller
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* may then decide what to do with the transfer. If the
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* range pointer is NULL, it is ignored.
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*/
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struct arm32_dma_range *_ranges;
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int _nranges;
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/*
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* Opaque cookie for use by back-end.
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*/
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void *_cookie;
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/*
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* DMA mapping methods.
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*/
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int (*_dmamap_create)(bus_dma_tag_t, bus_size_t, int,
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bus_size_t, bus_size_t, int, bus_dmamap_t *);
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void (*_dmamap_destroy)(bus_dma_tag_t, bus_dmamap_t);
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int (*_dmamap_load)(bus_dma_tag_t, bus_dmamap_t, void *,
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bus_size_t, struct proc *, int);
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int (*_dmamap_load_mbuf)(bus_dma_tag_t, bus_dmamap_t,
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struct mbuf *, int);
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int (*_dmamap_load_uio)(bus_dma_tag_t, bus_dmamap_t,
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struct uio *, int);
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int (*_dmamap_load_raw)(bus_dma_tag_t, bus_dmamap_t,
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bus_dma_segment_t *, int, bus_size_t, int);
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void (*_dmamap_unload)(bus_dma_tag_t, bus_dmamap_t);
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void (*_dmamap_sync_pre)(bus_dma_tag_t, bus_dmamap_t,
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bus_addr_t, bus_size_t, int);
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void (*_dmamap_sync_post)(bus_dma_tag_t, bus_dmamap_t,
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bus_addr_t, bus_size_t, int);
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/*
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* DMA memory utility functions.
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*/
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int (*_dmamem_alloc)(bus_dma_tag_t, bus_size_t, bus_size_t,
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bus_size_t, bus_dma_segment_t *, int, int *, int);
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void (*_dmamem_free)(bus_dma_tag_t,
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bus_dma_segment_t *, int);
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int (*_dmamem_map)(bus_dma_tag_t, bus_dma_segment_t *,
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int, size_t, void **, int);
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void (*_dmamem_unmap)(bus_dma_tag_t, void *, size_t);
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paddr_t (*_dmamem_mmap)(bus_dma_tag_t, bus_dma_segment_t *,
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int, off_t, int, int);
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/*
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* DMA tag utility functions
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*/
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int (*_dmatag_subregion)(bus_dma_tag_t, bus_addr_t, bus_addr_t,
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bus_dma_tag_t *, int);
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void (*_dmatag_destroy)(bus_dma_tag_t);
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/*
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* State for bounce buffers
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*/
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int _tag_needs_free;
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int (*_may_bounce)(bus_dma_tag_t, bus_dmamap_t, int, int *);
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};
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/*
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* bus_dmamap_t
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*
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* Describes a DMA mapping.
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*/
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struct arm32_bus_dmamap {
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/*
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* PRIVATE MEMBERS: not for use by machine-independent code.
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*/
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bus_size_t _dm_size; /* largest DMA transfer mappable */
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int _dm_segcnt; /* number of segs this map can map */
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bus_size_t _dm_maxmaxsegsz; /* fixed largest possible segment */
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bus_size_t _dm_boundary; /* don't cross this */
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int _dm_flags; /* misc. flags */
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void *_dm_origbuf; /* pointer to original buffer */
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int _dm_buftype; /* type of buffer */
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struct vmspace *_dm_vmspace; /* vmspace that owns the mapping */
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void *_dm_cookie; /* cookie for bus-specific functions */
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/*
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* PUBLIC MEMBERS: these are used by machine-independent code.
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*/
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bus_size_t dm_maxsegsz; /* largest possible segment */
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bus_size_t dm_mapsize; /* size of the mapping */
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int dm_nsegs; /* # valid segments in mapping */
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bus_dma_segment_t dm_segs[1]; /* segments; variable length */
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};
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/* _dm_buftype */
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#define _BUS_DMA_BUFTYPE_INVALID 0
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#define _BUS_DMA_BUFTYPE_LINEAR 1
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#define _BUS_DMA_BUFTYPE_MBUF 2
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#define _BUS_DMA_BUFTYPE_UIO 3
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#define _BUS_DMA_BUFTYPE_RAW 4
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#ifdef _ARM32_BUS_DMA_PRIVATE
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#define _BUS_AVAIL_END physical_end
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/*
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* Cookie used for bounce buffers. A pointer to one of these it stashed in
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* the DMA map.
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*/
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struct arm32_bus_dma_cookie {
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int id_flags; /* flags; see below */
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/*
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* Information about the original buffer used during
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* DMA map syncs. Note that origibuflen is only used
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* for ID_BUFTYPE_LINEAR.
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*/
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union {
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void *un_origbuf; /* pointer to orig buffer if
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bouncing */
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char *un_linearbuf;
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struct mbuf *un_mbuf;
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struct uio *un_uio;
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} id_origbuf_un;
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#define id_origbuf id_origbuf_un.un_origbuf
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#define id_origlinearbuf id_origbuf_un.un_linearbuf
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#define id_origmbuf id_origbuf_un.un_mbuf
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#define id_origuio id_origbuf_un.un_uio
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bus_size_t id_origbuflen; /* ...and size */
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void *id_bouncebuf; /* pointer to the bounce buffer */
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bus_size_t id_bouncebuflen; /* ...and size */
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int id_nbouncesegs; /* number of valid bounce segs */
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bus_dma_segment_t id_bouncesegs[0]; /* array of bounce buffer
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physical memory segments */
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};
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/* id_flags */
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#define _BUS_DMA_IS_BOUNCING 0x04 /* is bouncing current xfer */
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#define _BUS_DMA_HAS_BOUNCE 0x02 /* has bounce buffers */
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#endif /* _ARM32_BUS_DMA_PRIVATE */
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#define _BUS_DMA_MIGHT_NEED_BOUNCE 0x01 /* may need bounce buffers */
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#endif /* _ARM32_BUS_DEFS_H_ */
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