cf9a4ec79b
Coverity was flagging a recursive include between kernel.h and cpulocals.h. As cpulocals.h also included proc.h, we can move that include statement into kernel.h, and clean up the source files' include statements accordingly.
577 lines
12 KiB
C
577 lines
12 KiB
C
/* system dependent functions for use inside the whole kernel. */
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#include "kernel/kernel.h"
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#include <unistd.h>
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#include <ctype.h>
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#include <string.h>
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#include <machine/cmos.h>
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#include <machine/bios.h>
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#include <minix/portio.h>
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#include <minix/cpufeature.h>
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#include <assert.h>
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#include <signal.h>
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#include <machine/vm.h>
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#include <minix/u64.h>
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#include "archconst.h"
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#include "arch_proto.h"
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#include "serial.h"
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#include "oxpcie.h"
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#include "direct_utils.h"
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#include <machine/multiboot.h>
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#include "glo.h"
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#ifdef USE_APIC
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#include "apic.h"
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#endif
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#ifdef USE_ACPI
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#include "acpi.h"
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#endif
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static int osfxsr_feature; /* FXSAVE/FXRSTOR instructions support (SSEx) */
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/* set MP and NE flags to handle FPU exceptions in native mode. */
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#define CR0_MP_NE 0x0022
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/* set CR4.OSFXSR[bit 9] if FXSR is supported. */
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#define CR4_OSFXSR (1L<<9)
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/* set OSXMMEXCPT[bit 10] if we provide #XM handler. */
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#define CR4_OSXMMEXCPT (1L<<10)
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void * k_stacks;
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static void ser_debug(int c);
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#ifdef CONFIG_SMP
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static void ser_dump_proc_cpu(void);
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#endif
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#if !CONFIG_OXPCIE
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static void ser_init(void);
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#endif
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void fpu_init(void)
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{
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unsigned short cw, sw;
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fninit();
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sw = fnstsw();
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fnstcw(&cw);
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if((sw & 0xff) == 0 &&
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(cw & 0x103f) == 0x3f) {
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/* We have some sort of FPU, but don't check exact model.
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* Set CR0_NE and CR0_MP to handle fpu exceptions
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* in native mode. */
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write_cr0(read_cr0() | CR0_MP_NE);
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get_cpulocal_var(fpu_presence) = 1;
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if(_cpufeature(_CPUF_I386_FXSR)) {
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u32_t cr4 = read_cr4() | CR4_OSFXSR; /* Enable FXSR. */
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/* OSXMMEXCPT if supported
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* FXSR feature can be available without SSE
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*/
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if(_cpufeature(_CPUF_I386_SSE))
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cr4 |= CR4_OSXMMEXCPT;
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write_cr4(cr4);
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osfxsr_feature = 1;
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} else {
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osfxsr_feature = 0;
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}
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} else {
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/* No FPU presents. */
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get_cpulocal_var(fpu_presence) = 0;
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osfxsr_feature = 0;
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return;
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}
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}
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void save_local_fpu(struct proc *pr, int retain)
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{
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char *state = pr->p_seg.fpu_state;
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/* Save process FPU context. If the 'retain' flag is set, keep the FPU
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* state as is. If the flag is not set, the state is undefined upon
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* return, and the caller is responsible for reloading a proper state.
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*/
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if(!is_fpu())
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return;
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assert(state);
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if(osfxsr_feature) {
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fxsave(state);
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} else {
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fnsave(state);
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if (retain)
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(void) frstor(state);
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}
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}
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void save_fpu(struct proc *pr)
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{
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#ifdef CONFIG_SMP
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if (cpuid != pr->p_cpu) {
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int stopped;
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/* remember if the process was already stopped */
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stopped = RTS_ISSET(pr, RTS_PROC_STOP);
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/* stop the remote process and force its context to be saved */
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smp_schedule_stop_proc_save_ctx(pr);
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/*
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* If the process wasn't stopped let the process run again. The
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* process is kept block by the fact that the kernel cannot run
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* on its cpu
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*/
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if (!stopped)
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RTS_UNSET(pr, RTS_PROC_STOP);
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return;
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}
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#endif
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if (get_cpulocal_var(fpu_owner) == pr) {
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disable_fpu_exception();
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save_local_fpu(pr, TRUE /*retain*/);
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}
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}
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/* reserve a chunk of memory for fpu state; every one has to
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* be FPUALIGN-aligned.
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*/
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static char fpu_state[NR_PROCS][FPU_XFP_SIZE] __aligned(FPUALIGN);
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void arch_proc_reset(struct proc *pr)
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{
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char *v = NULL;
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assert(pr->p_nr < NR_PROCS);
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if(pr->p_nr >= 0) {
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v = fpu_state[pr->p_nr];
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/* verify alignment */
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assert(!((vir_bytes)v % FPUALIGN));
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/* initialize state */
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memset(v, 0, FPU_XFP_SIZE);
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}
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/* Clear process state. */
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memset(&pr->p_reg, 0, sizeof(pr->p_reg));
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if(iskerneln(pr->p_nr))
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pr->p_reg.psw = INIT_TASK_PSW;
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else
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pr->p_reg.psw = INIT_PSW;
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pr->p_seg.fpu_state = v;
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/* Initialize the fundamentals that are (initially) the same for all
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* processes - the segment selectors it gets to use.
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*/
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pr->p_reg.cs = USER_CS_SELECTOR;
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pr->p_reg.gs =
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pr->p_reg.fs =
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pr->p_reg.ss =
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pr->p_reg.es =
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pr->p_reg.ds = USER_DS_SELECTOR;
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}
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void arch_set_secondary_ipc_return(struct proc *p, u32_t val)
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{
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p->p_reg.bx = val;
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}
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int restore_fpu(struct proc *pr)
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{
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int failed;
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char *state = pr->p_seg.fpu_state;
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assert(state);
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if(!proc_used_fpu(pr)) {
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fninit();
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pr->p_misc_flags |= MF_FPU_INITIALIZED;
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} else {
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if(osfxsr_feature) {
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failed = fxrstor(state);
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} else {
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failed = frstor(state);
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}
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if (failed) return EINVAL;
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}
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return OK;
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}
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void cpu_identify(void)
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{
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u32_t eax, ebx, ecx, edx;
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unsigned cpu = cpuid;
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eax = 0;
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_cpuid(&eax, &ebx, &ecx, &edx);
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if (ebx == INTEL_CPUID_GEN_EBX && ecx == INTEL_CPUID_GEN_ECX &&
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edx == INTEL_CPUID_GEN_EDX) {
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cpu_info[cpu].vendor = CPU_VENDOR_INTEL;
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} else if (ebx == AMD_CPUID_GEN_EBX && ecx == AMD_CPUID_GEN_ECX &&
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edx == AMD_CPUID_GEN_EDX) {
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cpu_info[cpu].vendor = CPU_VENDOR_AMD;
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} else
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cpu_info[cpu].vendor = CPU_VENDOR_UNKNOWN;
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if (eax == 0)
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return;
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eax = 1;
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_cpuid(&eax, &ebx, &ecx, &edx);
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cpu_info[cpu].family = (eax >> 8) & 0xf;
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if (cpu_info[cpu].family == 0xf)
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cpu_info[cpu].family += (eax >> 20) & 0xff;
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cpu_info[cpu].model = (eax >> 4) & 0xf;
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if (cpu_info[cpu].model == 0xf || cpu_info[cpu].model == 0x6)
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cpu_info[cpu].model += ((eax >> 16) & 0xf) << 4 ;
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cpu_info[cpu].stepping = eax & 0xf;
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cpu_info[cpu].flags[0] = ecx;
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cpu_info[cpu].flags[1] = edx;
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}
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void arch_init(void)
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{
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/* FIXME stupid a.out
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* align the stacks in the stack are to the K_STACK_SIZE which is a
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* power of 2
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*/
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k_stacks = (void*) (((vir_bytes)&k_stacks_start + K_STACK_SIZE - 1) &
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~(K_STACK_SIZE - 1));
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#ifndef CONFIG_SMP
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/*
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* use stack 0 and cpu id 0 on a single processor machine, SMP
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* configuration does this in smp_init() for all cpus at once
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*/
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tss_init(0, get_k_stack_top(0));
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#endif
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#if !CONFIG_OXPCIE
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ser_init();
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#endif
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#ifdef USE_ACPI
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acpi_init();
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#endif
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#if defined(USE_APIC) && !defined(CONFIG_SMP)
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if (config_no_apic) {
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BOOT_VERBOSE(printf("APIC disabled, using legacy PIC\n"));
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}
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else if (!apic_single_cpu_init()) {
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BOOT_VERBOSE(printf("APIC not present, using legacy PIC\n"));
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}
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#endif
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/* Reserve some BIOS ranges */
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cut_memmap(&kinfo, BIOS_MEM_BEGIN, BIOS_MEM_END);
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cut_memmap(&kinfo, BASE_MEM_TOP, UPPER_MEM_END);
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}
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/*===========================================================================*
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* do_ser_debug *
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*===========================================================================*/
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void do_ser_debug()
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{
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u8_t c, lsr;
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#if CONFIG_OXPCIE
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{
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int oxin;
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if((oxin = oxpcie_in()) >= 0)
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ser_debug(oxin);
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}
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#endif
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lsr= inb(COM1_LSR);
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if (!(lsr & LSR_DR))
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return;
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c = inb(COM1_RBR);
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ser_debug(c);
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}
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static void ser_dump_queue_cpu(unsigned cpu)
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{
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int q;
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struct proc ** rdy_head;
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rdy_head = get_cpu_var(cpu, run_q_head);
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for(q = 0; q < NR_SCHED_QUEUES; q++) {
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struct proc *p;
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if(rdy_head[q]) {
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printf("%2d: ", q);
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for(p = rdy_head[q]; p; p = p->p_nextready) {
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printf("%s / %d ", p->p_name, p->p_endpoint);
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}
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printf("\n");
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}
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}
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}
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static void ser_dump_queues(void)
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{
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#ifdef CONFIG_SMP
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unsigned cpu;
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printf("--- run queues ---\n");
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for (cpu = 0; cpu < ncpus; cpu++) {
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printf("CPU %d :\n", cpu);
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ser_dump_queue_cpu(cpu);
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}
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#else
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ser_dump_queue_cpu(0);
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#endif
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}
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#ifdef CONFIG_SMP
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static void dump_bkl_usage(void)
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{
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unsigned cpu;
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printf("--- BKL usage ---\n");
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for (cpu = 0; cpu < ncpus; cpu++) {
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printf("cpu %3d kernel ticks 0x%x%08x bkl ticks 0x%x%08x succ %d tries %d\n", cpu,
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ex64hi(kernel_ticks[cpu]),
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ex64lo(kernel_ticks[cpu]),
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ex64hi(bkl_ticks[cpu]),
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ex64lo(bkl_ticks[cpu]),
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bkl_succ[cpu], bkl_tries[cpu]);
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}
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}
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static void reset_bkl_usage(void)
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{
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memset(kernel_ticks, 0, sizeof(kernel_ticks));
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memset(bkl_ticks, 0, sizeof(bkl_ticks));
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memset(bkl_tries, 0, sizeof(bkl_tries));
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memset(bkl_succ, 0, sizeof(bkl_succ));
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}
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#endif
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static void ser_debug(const int c)
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{
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serial_debug_active = 1;
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switch(c)
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{
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case 'Q':
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minix_shutdown(NULL);
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NOT_REACHABLE;
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#ifdef CONFIG_SMP
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case 'B':
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dump_bkl_usage();
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break;
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case 'b':
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reset_bkl_usage();
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break;
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#endif
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case '1':
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ser_dump_proc();
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break;
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case '2':
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ser_dump_queues();
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break;
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#ifdef CONFIG_SMP
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case '4':
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ser_dump_proc_cpu();
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break;
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#endif
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#if DEBUG_TRACE
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#define TOGGLECASE(ch, flag) \
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case ch: { \
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if(verboseflags & flag) { \
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verboseflags &= ~flag; \
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printf("%s disabled\n", #flag); \
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} else { \
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verboseflags |= flag; \
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printf("%s enabled\n", #flag); \
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} \
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break; \
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}
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TOGGLECASE('8', VF_SCHEDULING)
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TOGGLECASE('9', VF_PICKPROC)
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#endif
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#ifdef USE_APIC
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case 'I':
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dump_apic_irq_state();
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break;
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#endif
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}
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serial_debug_active = 0;
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}
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#if DEBUG_SERIAL
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void ser_dump_proc()
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{
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struct proc *pp;
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for (pp= BEG_PROC_ADDR; pp < END_PROC_ADDR; pp++)
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{
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if (isemptyp(pp))
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continue;
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print_proc_recursive(pp);
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}
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}
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#ifdef CONFIG_SMP
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static void ser_dump_proc_cpu(void)
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{
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struct proc *pp;
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unsigned cpu;
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for (cpu = 0; cpu < ncpus; cpu++) {
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printf("CPU %d processes : \n", cpu);
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for (pp= BEG_USER_ADDR; pp < END_PROC_ADDR; pp++) {
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if (isemptyp(pp) || pp->p_cpu != cpu)
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continue;
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print_proc(pp);
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}
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}
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}
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#endif
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#endif /* DEBUG_SERIAL */
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#if SPROFILE
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int arch_init_profile_clock(const u32_t freq)
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{
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int r;
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/* Set CMOS timer frequency. */
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outb(RTC_INDEX, RTC_REG_A);
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outb(RTC_IO, RTC_A_DV_OK | freq);
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/* Enable CMOS timer interrupts. */
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outb(RTC_INDEX, RTC_REG_B);
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r = inb(RTC_IO);
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outb(RTC_INDEX, RTC_REG_B);
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outb(RTC_IO, r | RTC_B_PIE);
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/* Mandatory read of CMOS register to enable timer interrupts. */
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outb(RTC_INDEX, RTC_REG_C);
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inb(RTC_IO);
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return CMOS_CLOCK_IRQ;
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}
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void arch_stop_profile_clock(void)
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{
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int r;
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/* Disable CMOS timer interrupts. */
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outb(RTC_INDEX, RTC_REG_B);
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r = inb(RTC_IO);
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outb(RTC_INDEX, RTC_REG_B);
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outb(RTC_IO, r & ~RTC_B_PIE);
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}
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void arch_ack_profile_clock(void)
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{
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/* Mandatory read of CMOS register to re-enable timer interrupts. */
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outb(RTC_INDEX, RTC_REG_C);
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inb(RTC_IO);
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}
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#endif
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void arch_do_syscall(struct proc *proc)
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{
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/* do_ipc assumes that it's running because of the current process */
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assert(proc == get_cpulocal_var(proc_ptr));
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/* Make the system call, for real this time. */
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proc->p_reg.retreg =
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do_ipc(proc->p_reg.cx, proc->p_reg.retreg, proc->p_reg.bx);
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}
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struct proc * arch_finish_switch_to_user(void)
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{
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char * stk;
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struct proc * p;
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#ifdef CONFIG_SMP
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stk = (char *)tss[cpuid].sp0;
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#else
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stk = (char *)tss[0].sp0;
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#endif
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/* set pointer to the process to run on the stack */
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p = get_cpulocal_var(proc_ptr);
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*((reg_t *)stk) = (reg_t) p;
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/* make sure IF is on in FLAGS so that interrupts won't be disabled
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* once p's context is restored. this should not be possible.
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*/
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assert(p->p_reg.psw & (1L << 9));
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return p;
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}
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void fpu_sigcontext(struct proc *pr, struct sigframe *fr, struct sigcontext *sc)
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{
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int fp_error;
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if (osfxsr_feature) {
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fp_error = sc->sc_fpu_state.xfp_regs.fp_status &
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~sc->sc_fpu_state.xfp_regs.fp_control;
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} else {
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fp_error = sc->sc_fpu_state.fpu_regs.fp_status &
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~sc->sc_fpu_state.fpu_regs.fp_control;
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}
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if (fp_error & 0x001) { /* Invalid op */
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/*
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* swd & 0x240 == 0x040: Stack Underflow
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* swd & 0x240 == 0x240: Stack Overflow
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* User must clear the SF bit (0x40) if set
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*/
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fr->sf_code = FPE_FLTINV;
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} else if (fp_error & 0x004) {
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fr->sf_code = FPE_FLTDIV; /* Divide by Zero */
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} else if (fp_error & 0x008) {
|
|
fr->sf_code = FPE_FLTOVF; /* Overflow */
|
|
} else if (fp_error & 0x012) {
|
|
fr->sf_code = FPE_FLTUND; /* Denormal, Underflow */
|
|
} else if (fp_error & 0x020) {
|
|
fr->sf_code = FPE_FLTRES; /* Precision */
|
|
} else {
|
|
fr->sf_code = 0; /* XXX - probably should be used for FPE_INTOVF or
|
|
* FPE_INTDIV */
|
|
}
|
|
}
|
|
|
|
#if !CONFIG_OXPCIE
|
|
static void ser_init(void)
|
|
{
|
|
unsigned char lcr;
|
|
unsigned divisor;
|
|
|
|
/* keep BIOS settings if cttybaud is not set */
|
|
if (kinfo.serial_debug_baud <= 0) return;
|
|
|
|
/* set DLAB to make baud accessible */
|
|
lcr = LCR_8BIT | LCR_1STOP | LCR_NPAR;
|
|
outb(COM1_LCR, lcr | LCR_DLAB);
|
|
|
|
/* set baud rate */
|
|
divisor = UART_BASE_FREQ / kinfo.serial_debug_baud;
|
|
if (divisor < 1) divisor = 1;
|
|
if (divisor > 65535) divisor = 65535;
|
|
|
|
outb(COM1_DLL, divisor & 0xff);
|
|
outb(COM1_DLM, (divisor >> 8) & 0xff);
|
|
|
|
/* clear DLAB */
|
|
outb(COM1_LCR, lcr);
|
|
}
|
|
#endif
|
|
|