655 lines
16 KiB
C
655 lines
16 KiB
C
/* Best viewed with tabsize 4 */
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/* Ensoniq ES1370 driver
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*
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* aka AudioPCI '97
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*
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* This is the main file of the ES1370 sound driver. There is no main function
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* over here, instead the main function is located in the generic dma driver.
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* All this driver does is implement the interface audio/audio_fw.h. All
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* functions having the prefix 'drv_' are dictated by audio/audio_fw.h. The
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* function prototypes you see below define a set of private helper functions.
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* Control over the AK4531 codec is delegated ak4531.c.
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*
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* September 2007 ES1370 driver (Pieter Hijma),
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* based on ES1371 driver by Laurens Bronwasser
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*/
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#include <machine/pci.h>
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#include <minix/audio_fw.h>
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#include "es1370.h"
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#include "ak4531.h"
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#include "pci_helper.h"
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/* reg(n) will be the device specific addresses */
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#define reg(n) (dev.base + (n))
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/* prototypes of private functions */
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static int detect_hw(void);
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static int disable_int(int sub_dev);
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static int set_stereo(u32_t stereo, int sub_dev);
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static int set_bits(u32_t nr_of_bits, int sub_dev);
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static int set_sample_rate(u32_t rate, int sub_dev);
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static int set_sign(u32_t val, int sub_dev);
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static int get_max_frag_size(u32_t * val, int *len, int sub_dev);
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static int set_frag_size(u32_t fragment_size, int sub_dev);
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static int set_int_cnt(int sub_dev);
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static int free_buf(u32_t *val, int *len, int sub_dev);
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static int get_samples_in_buf(u32_t *val, int *len, int sub_dev);
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static int get_set_volume(struct volume_level *level, int *len, int
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sub_dev, int flag);
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static int reset(int sub_dev);
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DEV_STRUCT dev;
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aud_sub_dev_conf_t aud_conf[4];
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sub_dev_t sub_dev[4];
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special_file_t special_file[4];
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drv_t drv;
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int drv_init(void) {
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drv.DriverName = DRIVER_NAME;
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drv.NrOfSubDevices = 4;
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drv.NrOfSpecialFiles = 4;
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sub_dev[DAC1_CHAN].readable = 0;
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sub_dev[DAC1_CHAN].writable = 1;
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sub_dev[DAC1_CHAN].DmaSize = 64 * 1024;
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sub_dev[DAC1_CHAN].NrOfDmaFragments = 2;
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sub_dev[DAC1_CHAN].MinFragmentSize = 1024;
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sub_dev[DAC1_CHAN].NrOfExtraBuffers = 4;
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sub_dev[ADC1_CHAN].readable = 1;
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sub_dev[ADC1_CHAN].writable = 0;
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sub_dev[ADC1_CHAN].DmaSize = 64 * 1024;
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sub_dev[ADC1_CHAN].NrOfDmaFragments = 2;
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sub_dev[ADC1_CHAN].MinFragmentSize = 1024;
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sub_dev[ADC1_CHAN].NrOfExtraBuffers = 4;
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sub_dev[MIXER].writable = 0;
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sub_dev[MIXER].readable = 0;
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sub_dev[DAC2_CHAN].readable = 0;
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sub_dev[DAC2_CHAN].writable = 1;
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sub_dev[DAC2_CHAN].DmaSize = 64 * 1024;
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sub_dev[DAC2_CHAN].NrOfDmaFragments = 2;
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sub_dev[DAC2_CHAN].MinFragmentSize = 1024;
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sub_dev[DAC2_CHAN].NrOfExtraBuffers = 4;
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special_file[0].minor_dev_nr = 0;
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special_file[0].write_chan = DAC1_CHAN;
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special_file[0].read_chan = NO_CHANNEL;
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special_file[0].io_ctl = DAC1_CHAN;
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special_file[1].minor_dev_nr = 1;
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special_file[1].write_chan = NO_CHANNEL;
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special_file[1].read_chan = ADC1_CHAN;
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special_file[1].io_ctl = ADC1_CHAN;
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special_file[2].minor_dev_nr = 2;
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special_file[2].write_chan = NO_CHANNEL;
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special_file[2].read_chan = NO_CHANNEL;
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special_file[2].io_ctl = MIXER;
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special_file[3].minor_dev_nr = 3;
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special_file[3].write_chan = DAC2_CHAN;
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special_file[3].read_chan = NO_CHANNEL;
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special_file[3].io_ctl = DAC2_CHAN;
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return OK;
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}
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int drv_init_hw (void) {
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u16_t i, j;
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u16_t chip_sel_ctrl_reg;
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/* First, detect the hardware */
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if (detect_hw() != OK) {
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return EIO;
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}
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/* PCI command register
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* enable the SERR# driver, PCI bus mastering and I/O access
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*/
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pci_attr_w16 (dev.devind, PCI_CR, SERR_EN|PCI_MASTER|IO_ACCESS);
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/* turn everything off */
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pci_outl(reg(CHIP_SEL_CTRL), 0x0UL);
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/* turn off legacy (legacy control is undocumented) */
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pci_outl(reg(LEGACY), 0x0UL);
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pci_outl(reg(LEGACY+4), 0x0UL);
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/* turn off serial interface */
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pci_outl(reg(SERIAL_INTERFACE_CTRL), 0x0UL);
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/*pci_outl(reg(SERIAL_INTERFACE_CTRL), 0x3UL);*/
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/* enable the codec */
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chip_sel_ctrl_reg = pci_inw(reg(CHIP_SEL_CTRL));
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chip_sel_ctrl_reg |= XCTL0 | CDC_EN;
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pci_outw(reg(CHIP_SEL_CTRL), chip_sel_ctrl_reg);
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/* initialize the codec */
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if (ak4531_init(reg(CODEC_WRITE_ADDRESS),
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reg(INTERRUPT_STATUS), CWRIP, reg(0)) < 0) {
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return EINVAL;
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}
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/* clear all the memory */
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for (i = 0; i < 0x10; ++i) {
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pci_outb(reg(MEM_PAGE), i);
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for (j = 0; j < 0x10; j += 4) {
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pci_outl (reg(MEMORY) + j, 0x0UL);
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}
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}
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/* initialize variables for each sub_device */
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for (i = 0; i < drv.NrOfSubDevices; i++) {
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if(i != MIXER) {
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aud_conf[i].busy = 0;
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aud_conf[i].stereo = DEFAULT_STEREO;
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aud_conf[i].sample_rate = DEFAULT_RATE;
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aud_conf[i].nr_of_bits = DEFAULT_NR_OF_BITS;
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aud_conf[i].sign = DEFAULT_SIGNED;
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aud_conf[i].fragment_size =
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sub_dev[i].DmaSize / sub_dev[i].NrOfDmaFragments;
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}
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}
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return OK;
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}
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static int detect_hw(void) {
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u32_t device;
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int devind;
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u16_t v_id, d_id;
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/* detect_hw tries to find device and get IRQ and base address
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with a little (much) help from the PCI library.
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This code is quite device independent and you can copy it.
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(just make sure to get the bugs out first)*/
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pci_init();
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/* get first device and then search through the list */
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device = pci_first_dev(&devind, &v_id, &d_id);
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while( device > 0 ) {
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/* if we have a match...break */
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if (v_id == VENDOR_ID && d_id == DEVICE_ID) break;
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device = pci_next_dev(&devind, &v_id, &d_id);
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}
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/* did we find anything? */
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if (v_id != VENDOR_ID || d_id != DEVICE_ID) {
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return EIO;
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}
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pci_reserve(devind);
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dev.name = pci_dev_name(v_id, d_id);
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/* get base address of our device, ignore least signif. bit
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this last bit thing could be device dependent, i don't know */
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dev.base = pci_attr_r32(devind, PCI_BAR) & 0xfffffffe;
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/* get IRQ */
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dev.irq = pci_attr_r8(devind, PCI_ILR);
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dev.revision = pci_attr_r8(devind, PCI_REV);
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dev.d_id = d_id;
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dev.v_id = v_id;
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dev.devind = devind; /* pci device identifier */
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return OK;
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}
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static int reset(int chan) {
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drv_stop(chan);
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sub_dev[chan].OutOfData = 1;
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return OK;
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}
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int drv_reset() {
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return OK;
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}
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int drv_start(int sub_dev, int UNUSED(DmaMode)) {
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u32_t enable_bit, result = 0;
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/* Write default values to device in case user failed to configure.
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If user did configure properly, everything is written twice.
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please raise your hand if you object against to this strategy...*/
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result |= set_sample_rate(aud_conf[sub_dev].sample_rate, sub_dev);
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result |= set_stereo(aud_conf[sub_dev].stereo, sub_dev);
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result |= set_bits(aud_conf[sub_dev].nr_of_bits, sub_dev);
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result |= set_sign(aud_conf[sub_dev].sign, sub_dev);
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/* set the interrupt count */
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result |= set_int_cnt(sub_dev);
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if (result) {
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return EIO;
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}
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/* if device currently paused, resume */
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drv_resume(sub_dev);
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switch(sub_dev) {
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case ADC1_CHAN: enable_bit = ADC1_EN;break;
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case DAC1_CHAN: enable_bit = DAC1_EN;break;
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case DAC2_CHAN: enable_bit = DAC2_EN;break;
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default: return EINVAL;
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}
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/* enable interrupts from 'sub device' */
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drv_reenable_int(sub_dev);
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/* this means play!!! */
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pci_outw(reg(CHIP_SEL_CTRL), pci_inw(reg(CHIP_SEL_CTRL)) | enable_bit);
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aud_conf[sub_dev].busy = 1;
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return OK;
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}
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int drv_stop(int sub_dev)
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{
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u32_t enable_bit;
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int status;
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switch(sub_dev) {
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case ADC1_CHAN: enable_bit = ADC1_EN;break;
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case DAC1_CHAN: enable_bit = DAC1_EN;break;
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case DAC2_CHAN: enable_bit = DAC2_EN;break;
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default: return EINVAL;
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}
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/* stop the specified channel */
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pci_outw(reg(CHIP_SEL_CTRL),
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pci_inw(reg(CHIP_SEL_CTRL)) & ~enable_bit);
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aud_conf[sub_dev].busy = 0;
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status = disable_int(sub_dev);
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return status;
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}
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/* all IO-ctl's sent to the upper driver are passed to this function */
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int drv_io_ctl(int request, void * val, int * len, int sub_dev) {
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int status;
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switch(request) {
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case DSPIORATE:
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status = set_sample_rate(*((u32_t *) val), sub_dev); break;
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case DSPIOSTEREO:
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status = set_stereo(*((u32_t *) val), sub_dev); break;
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case DSPIOBITS:
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status = set_bits(*((u32_t *) val), sub_dev); break;
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case DSPIOSIZE:
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status = set_frag_size(*((u32_t *) val), sub_dev); break;
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case DSPIOSIGN:
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status = set_sign(*((u32_t *) val), sub_dev); break;
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case DSPIOMAX:
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status = get_max_frag_size(val, len, sub_dev); break;
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case DSPIORESET:
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status = reset(sub_dev); break;
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case DSPIOFREEBUF:
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status = free_buf(val, len, sub_dev); break;
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case DSPIOSAMPLESINBUF:
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status = get_samples_in_buf(val, len, sub_dev); break;
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case DSPIOPAUSE:
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status = drv_pause(sub_dev); break;
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case DSPIORESUME:
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status = drv_resume(sub_dev); break;
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case MIXIOGETVOLUME:
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status = get_set_volume(val, len, sub_dev, 0); break;
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case MIXIOSETVOLUME:
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status = get_set_volume(val, len, sub_dev, 1); break;
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default:
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status = EINVAL; break;
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}
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return status;
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}
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int drv_get_irq(char *irq) {
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*irq = dev.irq;
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return OK;
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}
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int drv_get_frag_size(u32_t *frag_size, int sub_dev) {
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*frag_size = aud_conf[sub_dev].fragment_size;
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return OK;
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}
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int drv_set_dma(u32_t dma, u32_t length, int chan) {
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/* dma length in bytes,
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max is 64k long words for es1370 = 256k bytes */
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u32_t page, frame_count_reg, dma_add_reg;
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switch(chan) {
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case ADC1_CHAN: page = ADC_MEM_PAGE;
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frame_count_reg = ADC_BUFFER_SIZE;
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dma_add_reg = ADC_PCI_ADDRESS;
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break;
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case DAC1_CHAN: page = DAC_MEM_PAGE;
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frame_count_reg = DAC1_BUFFER_SIZE;
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dma_add_reg = DAC1_PCI_ADDRESS;
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break;
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case DAC2_CHAN: page = DAC_MEM_PAGE;
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frame_count_reg = DAC2_BUFFER_SIZE;
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dma_add_reg = DAC2_PCI_ADDRESS;
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break;
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default: return EIO;
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}
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pci_outb(reg(MEM_PAGE), page);
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pci_outl(reg(dma_add_reg), dma);
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/* device expects long word count in stead of bytes */
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length /= 4;
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/* It seems that register _CURRENT_COUNT is overwritten, but this is
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* the way to go. The register frame_count_reg is only longword
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* addressable.
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* It expects length -1
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*/
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pci_outl(reg(frame_count_reg), (u32_t) (length - 1));
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return OK;
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}
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/* return status of the interrupt summary bit */
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int drv_int_sum(void) {
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return pci_inl(reg(INTERRUPT_STATUS)) & INTR;
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}
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int drv_int(int sub_dev) {
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u32_t int_status;
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u32_t bit;
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/* return status of interrupt bit of specified channel*/
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switch (sub_dev) {
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case DAC1_CHAN: bit = DAC1; break;
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case DAC2_CHAN: bit = DAC2; break;
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case ADC1_CHAN: bit = ADC; break;
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default: return EINVAL;
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}
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int_status = pci_inl(reg(INTERRUPT_STATUS)) & bit;
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return int_status;
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}
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int drv_reenable_int(int chan) {
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u16_t ser_interface, int_en_bit;
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switch(chan) {
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case ADC1_CHAN: int_en_bit = R1_INT_EN; break;
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case DAC1_CHAN: int_en_bit = P1_INTR_EN; break;
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case DAC2_CHAN: int_en_bit = P2_INTR_EN; break;
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default: return EINVAL;
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}
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/* clear and reenable an interrupt */
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ser_interface = pci_inw(reg(SERIAL_INTERFACE_CTRL));
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pci_outw(reg(SERIAL_INTERFACE_CTRL), ser_interface & ~int_en_bit);
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pci_outw(reg(SERIAL_INTERFACE_CTRL), ser_interface | int_en_bit);
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return OK;
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}
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int drv_pause(int sub_dev) {
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u32_t pause_bit;
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disable_int(sub_dev); /* don't send interrupts */
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switch(sub_dev) {
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case DAC1_CHAN: pause_bit = P1_PAUSE;break;
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case DAC2_CHAN: pause_bit = P2_PAUSE;break;
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default: return EINVAL;
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}
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/* pause */
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pci_outl(reg(SERIAL_INTERFACE_CTRL),
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pci_inl(reg(SERIAL_INTERFACE_CTRL)) | pause_bit);
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return OK;
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}
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int drv_resume(int sub_dev) {
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u32_t pause_bit = 0;
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drv_reenable_int(sub_dev); /* enable interrupts */
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switch(sub_dev) {
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case DAC1_CHAN: pause_bit = P1_PAUSE;break;
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case DAC2_CHAN: pause_bit = P2_PAUSE;break;
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default: return EINVAL;
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}
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/* clear pause bit */
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pci_outl(reg(SERIAL_INTERFACE_CTRL),
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pci_inl(reg(SERIAL_INTERFACE_CTRL)) & ~pause_bit);
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return OK;
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}
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static int set_bits(u32_t nr_of_bits, int sub_dev) {
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/* set format bits for specified channel. */
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u16_t size_16_bit, ser_interface;
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switch(sub_dev) {
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case ADC1_CHAN: size_16_bit = R1_S_EB; break;
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case DAC1_CHAN: size_16_bit = P1_S_EB; break;
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case DAC2_CHAN: size_16_bit = P2_S_EB; break;
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default: return EINVAL;
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}
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ser_interface = pci_inw(reg(SERIAL_INTERFACE_CTRL));
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ser_interface &= ~size_16_bit;
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switch(nr_of_bits) {
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case 16: ser_interface |= size_16_bit;break;
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case 8: break;
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default: return EINVAL;
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}
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pci_outw(reg(SERIAL_INTERFACE_CTRL), ser_interface);
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aud_conf[sub_dev].nr_of_bits = nr_of_bits;
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return OK;
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}
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static int set_stereo(u32_t stereo, int sub_dev) {
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/* set format bits for specified channel. */
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u16_t stereo_bit, ser_interface;
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switch(sub_dev) {
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case ADC1_CHAN: stereo_bit = R1_S_MB; break;
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case DAC1_CHAN: stereo_bit = P1_S_MB; break;
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case DAC2_CHAN: stereo_bit = P2_S_MB; break;
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default: return EINVAL;
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}
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ser_interface = pci_inw(reg(SERIAL_INTERFACE_CTRL));
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ser_interface &= ~stereo_bit;
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if (stereo) {
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ser_interface |= stereo_bit;
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}
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pci_outw(reg(SERIAL_INTERFACE_CTRL), ser_interface);
|
|
aud_conf[sub_dev].stereo = stereo;
|
|
|
|
return OK;
|
|
}
|
|
|
|
|
|
static int set_sign(u32_t UNUSED(val), int UNUSED(sub_dev)) {
|
|
return OK;
|
|
}
|
|
|
|
|
|
static int set_frag_size(u32_t fragment_size, int sub_dev_nr) {
|
|
if (fragment_size > (sub_dev[sub_dev_nr].DmaSize /
|
|
sub_dev[sub_dev_nr].NrOfDmaFragments) ||
|
|
fragment_size < sub_dev[sub_dev_nr].MinFragmentSize) {
|
|
return EINVAL;
|
|
}
|
|
aud_conf[sub_dev_nr].fragment_size = fragment_size;
|
|
|
|
return OK;
|
|
}
|
|
|
|
|
|
static int set_sample_rate(u32_t rate, int sub_dev) {
|
|
/* currently only 44.1kHz */
|
|
u32_t controlRegister;
|
|
|
|
if (rate > MAX_RATE || rate < MIN_RATE) {
|
|
return EINVAL;
|
|
}
|
|
|
|
controlRegister = pci_inl(reg(CHIP_SEL_CTRL));
|
|
controlRegister |= FREQ_44K100;
|
|
pci_outl(reg(CHIP_SEL_CTRL), controlRegister);
|
|
|
|
aud_conf[sub_dev].sample_rate = rate;
|
|
|
|
return OK;
|
|
}
|
|
|
|
|
|
static int set_int_cnt(int chan) {
|
|
/* Write interrupt count for specified channel.
|
|
After <DspFragmentSize> bytes, an interrupt will be generated */
|
|
|
|
int sample_count;
|
|
u16_t int_cnt_reg;
|
|
|
|
if (aud_conf[chan].fragment_size >
|
|
(sub_dev[chan].DmaSize / sub_dev[chan].NrOfDmaFragments)
|
|
|| aud_conf[chan].fragment_size < sub_dev[chan].MinFragmentSize) {
|
|
return EINVAL;
|
|
}
|
|
|
|
switch(chan) {
|
|
case ADC1_CHAN: int_cnt_reg = ADC_SAMP_CT; break;
|
|
case DAC1_CHAN: int_cnt_reg = DAC1_SAMP_CT; break;
|
|
case DAC2_CHAN: int_cnt_reg = DAC2_SAMP_CT; break;
|
|
default: return EINVAL;
|
|
}
|
|
|
|
sample_count = aud_conf[chan].fragment_size;
|
|
|
|
/* adjust sample count according to sample format */
|
|
if( aud_conf[chan].stereo == TRUE ) sample_count >>= 1;
|
|
switch(aud_conf[chan].nr_of_bits) {
|
|
case 16: sample_count >>= 1;break;
|
|
case 8: break;
|
|
default: return EINVAL;
|
|
}
|
|
|
|
/* set the sample count - 1 for the specified channel. */
|
|
pci_outw(reg(int_cnt_reg), sample_count - 1);
|
|
|
|
return OK;
|
|
}
|
|
|
|
|
|
static int get_max_frag_size(u32_t * val, int * len, int sub_dev_nr) {
|
|
*len = sizeof(*val);
|
|
*val = (sub_dev[sub_dev_nr].DmaSize /
|
|
sub_dev[sub_dev_nr].NrOfDmaFragments);
|
|
return OK;
|
|
}
|
|
|
|
|
|
static int disable_int(int chan) {
|
|
u16_t ser_interface, int_en_bit;
|
|
|
|
switch(chan) {
|
|
case ADC1_CHAN: int_en_bit = R1_INT_EN; break;
|
|
case DAC1_CHAN: int_en_bit = P1_INTR_EN; break;
|
|
case DAC2_CHAN: int_en_bit = P2_INTR_EN; break;
|
|
default: return EINVAL;
|
|
}
|
|
/* clear the interrupt */
|
|
ser_interface = pci_inw(reg(SERIAL_INTERFACE_CTRL));
|
|
pci_outw(reg(SERIAL_INTERFACE_CTRL), ser_interface & ~int_en_bit);
|
|
return OK;
|
|
}
|
|
|
|
|
|
static int get_samples_in_buf (u32_t *samples_in_buf, int *len, int chan) {
|
|
u16_t samp_ct_reg;
|
|
u16_t curr_samp_ct_reg;
|
|
u16_t curr_samp_ct; /* counts back from SAMP_CT till 0 */
|
|
|
|
*len = sizeof(*samples_in_buf);
|
|
|
|
switch(chan) {
|
|
case ADC1_CHAN:
|
|
curr_samp_ct_reg = ADC_CURR_SAMP_CT;
|
|
samp_ct_reg = ADC_SAMP_CT; break;
|
|
case DAC1_CHAN:
|
|
curr_samp_ct_reg = DAC1_CURR_SAMP_CT;
|
|
samp_ct_reg = DAC1_SAMP_CT; break;
|
|
case DAC2_CHAN:
|
|
curr_samp_ct_reg = DAC2_CURR_SAMP_CT;
|
|
samp_ct_reg = DAC2_SAMP_CT; break;
|
|
default: return EINVAL;
|
|
}
|
|
|
|
/* TODO: is this inw useful? */
|
|
(void) pci_inw(reg(samp_ct_reg));
|
|
curr_samp_ct = pci_inw(reg(curr_samp_ct_reg));
|
|
|
|
*samples_in_buf = (u32_t) (sub_dev[chan].BufLength * 8192) +
|
|
curr_samp_ct;
|
|
|
|
return OK;
|
|
}
|
|
|
|
|
|
/* returns 1 if there are free buffers */
|
|
static int free_buf (u32_t *val, int *len, int sub_dev_nr) {
|
|
*len = sizeof(*val);
|
|
if (sub_dev[sub_dev_nr].BufLength ==
|
|
sub_dev[sub_dev_nr].NrOfExtraBuffers) {
|
|
*val = 0;
|
|
}
|
|
else {
|
|
*val = 1;
|
|
}
|
|
return OK;
|
|
}
|
|
|
|
|
|
static int get_set_volume(struct volume_level *level, int *len, int sub_dev,
|
|
int flag) {
|
|
*len = sizeof(struct volume_level);
|
|
if (sub_dev == MIXER) {
|
|
return ak4531_get_set_volume(level, flag);
|
|
}
|
|
else {
|
|
return EINVAL;
|
|
}
|
|
}
|