cf854041ce
- the PIC master and slave irq handlers don't pass the irq hook pointer but just the irq number. It gives a little bit more information to the C handler as the irq number is not lost - the irq code path is more achitecture independent. i386 hw interrupts are called irq and whereever the code is arch independent enough hw_intr_ functions are called to mask/unmask interrupts - the legacy PIC is not the only possible interrupt controller in the x86 world, therefore the intr_(un)mask functions were renamed to signal their functionality explicitly. APIC will add their own. - masking and unmasking PIC interrupt lines is removed from assembler and all the functionality is rewriten in C and moved to i8259.c - interrupt handlers have to unmask the interrupt line if all irq handlers are done. Assembler does not do it anymore
93 lines
3.3 KiB
C
Executable file
93 lines
3.3 KiB
C
Executable file
/* This file contains routines for initializing the 8259 interrupt controller:
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* put_irq_handler: register an interrupt handler
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* rm_irq_handler: deregister an interrupt handler
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* intr_handle: handle a hardware interrupt
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* intr_init: initialize the interrupt controller(s)
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*/
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#include "../../kernel.h"
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#include "../../proc.h"
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#include "proto.h"
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#include <minix/com.h>
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#include <minix/portio.h>
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#include <ibm/cpu.h>
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#define ICW1_AT 0x11 /* edge triggered, cascade, need ICW4 */
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#define ICW1_PC 0x13 /* edge triggered, no cascade, need ICW4 */
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#define ICW1_PS 0x19 /* level triggered, cascade, need ICW4 */
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#define ICW4_AT_SLAVE 0x01 /* not SFNM, not buffered, normal EOI, 8086 */
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#define ICW4_AT_MASTER 0x05 /* not SFNM, not buffered, normal EOI, 8086 */
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#define ICW4_PC_SLAVE 0x09 /* not SFNM, buffered, normal EOI, 8086 */
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#define ICW4_PC_MASTER 0x0D /* not SFNM, buffered, normal EOI, 8086 */
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#define set_vec(nr, addr) ((void)0)
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/*===========================================================================*
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* intr_init *
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*===========================================================================*/
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PUBLIC int intr_init(mine)
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int mine;
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{
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/* Initialize the 8259s, finishing with all interrupts disabled. This is
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* only done in protected mode, in real mode we don't touch the 8259s, but
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* use the BIOS locations instead. The flag "mine" is set if the 8259s are
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* to be programmed for MINIX, or to be reset to what the BIOS expects.
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*/
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int i;
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intr_disable();
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/* The AT and newer PS/2 have two interrupt controllers, one master,
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* one slaved at IRQ 2. (We don't have to deal with the PC that
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* has just one controller, because it must run in real mode.)
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*/
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outb( INT_CTL, machine.ps_mca ? ICW1_PS : ICW1_AT);
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outb( INT_CTLMASK, mine ? IRQ0_VECTOR : BIOS_IRQ0_VEC);
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/* ICW2 for master */
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outb( INT_CTLMASK, (1 << CASCADE_IRQ));
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/* ICW3 tells slaves */
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outb( INT_CTLMASK, ICW4_AT_MASTER);
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outb( INT_CTLMASK, ~(1 << CASCADE_IRQ)); /* IRQ 0-7 mask */
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outb( INT2_CTL, machine.ps_mca ? ICW1_PS : ICW1_AT);
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outb( INT2_CTLMASK, mine ? IRQ8_VECTOR : BIOS_IRQ8_VEC);
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/* ICW2 for slave */
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outb( INT2_CTLMASK, CASCADE_IRQ); /* ICW3 is slave nr */
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outb( INT2_CTLMASK, ICW4_AT_SLAVE);
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outb( INT2_CTLMASK, ~0); /* IRQ 8-15 mask */
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/* Copy the BIOS vectors from the BIOS to the Minix location, so we
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* can still make BIOS calls without reprogramming the i8259s.
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*/
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#if IRQ0_VECTOR != BIOS_IRQ0_VEC
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phys_copy(BIOS_VECTOR(0) * 4L, VECTOR(0) * 4L, 8 * 4L);
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#endif
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#if IRQ8_VECTOR != BIOS_IRQ8_VEC
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phys_copy(BIOS_VECTOR(8) * 4L, VECTOR(8) * 4L, 8 * 4L);
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#endif
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return OK;
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}
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/*===========================================================================*
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* intr_disabled *
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*===========================================================================*/
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PUBLIC int intr_disabled(void)
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{
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if(!(read_cpu_flags() & X86_FLAG_I))
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return 1;
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return 0;
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}
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PUBLIC void irq_8259_unmask(int irq)
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{
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unsigned ctl_mask = irq < 8 ? INT_CTLMASK : INT2_CTLMASK;
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outb(ctl_mask, inb(ctl_mask) & ~(1 << (irq & 0x7)));
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}
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PUBLIC void irq_8259_mask(int irq)
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{
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unsigned ctl_mask = irq < 8 ? INT_CTLMASK : INT2_CTLMASK;
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outb(ctl_mask, inb(ctl_mask) | (1 << (irq & 0x7)));
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}
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