b4d909d415
This patch separates the character and block driver communication protocols. The old character protocol remains the same, but a new block protocol is introduced. The libdriver library is replaced by two new libraries: libchardriver and libblockdriver. Their exposed API, and drivers that use them, have been updated accordingly. Together, libbdev and libblockdriver now completely abstract away the message format used by the block protocol. As the memory driver is both a character and a block device driver, it now implements its own message loop. The most important semantic change made to the block protocol is that it is no longer possible to return both partial results and an error for a single transfer. This simplifies the interaction between the caller and the driver, as the I/O vector no longer needs to be copied back. Also, drivers are now no longer supposed to decide based on the layout of the I/O vector when a transfer should be cut short. Put simply, transfers are now supposed to either succeed completely, or result in an error. After this patch, the state of the various pieces is as follows: - block protocol: stable - libbdev API: stable for synchronous communication - libblockdriver API: needs slight revision (the drvlib/partition API in particular; the threading API will also change shortly) - character protocol: needs cleanup - libchardriver API: needs cleanup accordingly - driver restarts: largely unsupported until endpoint changes are reintroduced As a side effect, this patch eliminates several bugs, hacks, and gcc -Wall and -W warnings all over the place. It probably introduces a few new ones, too. Update warning: this patch changes the protocol between MFS and disk drivers, so in order to use old/new images, the MFS from the ramdisk must be used to mount all file systems.
225 lines
10 KiB
C
225 lines
10 KiB
C
#include <minix/drivers.h>
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#include <minix/blockdriver.h>
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#include <minix/drvlib.h>
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#define VERBOSE 0 /* display identify messages during boot */
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#define ENABLE_ATAPI 1 /* add ATAPI cd-rom support to driver */
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#define ATAPI_DEBUG 0 /* To debug ATAPI code. */
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/* I/O Ports used by winchester disk controllers. */
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/* Read and write registers */
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#define REG_CMD_BASE0 0x1F0 /* command base register of controller 0 */
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#define REG_CMD_BASE1 0x170 /* command base register of controller 1 */
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#define REG_CTL_BASE0 0x3F6 /* control base register of controller 0 */
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#define REG_CTL_BASE1 0x376 /* control base register of controller 1 */
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#define PCI_CTL_OFF 2 /* Offset of control registers from BAR2 */
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#define PCI_DMA_2ND_OFF 8 /* Offset of DMA registers from BAR4 for
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* secondary channel
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*/
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#define REG_DATA 0 /* data register (offset from the base reg.) */
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#define REG_PRECOMP 1 /* start of write precompensation */
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#define REG_COUNT 2 /* sectors to transfer */
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#define REG_SECTOR 3 /* sector number */
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#define REG_CYL_LO 4 /* low byte of cylinder number */
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#define REG_CYL_HI 5 /* high byte of cylinder number */
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#define REG_LDH 6 /* lba, drive and head */
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#define LDH_DEFAULT 0xA0 /* ECC enable, 512 bytes per sector */
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#define LDH_LBA 0x40 /* Use LBA addressing */
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#define LDH_DEV 0x10 /* Drive 1 iff set */
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#define ldh_init(drive) (LDH_DEFAULT | ((drive) << 4))
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/* Read only registers */
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#define REG_STATUS 7 /* status */
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#define STATUS_BSY 0x80 /* controller busy */
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#define STATUS_RDY 0x40 /* drive ready */
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#define STATUS_WF 0x20 /* write fault */
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#define STATUS_SC 0x10 /* seek complete (obsolete) */
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#define STATUS_DRQ 0x08 /* data transfer request */
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#define STATUS_CRD 0x04 /* corrected data */
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#define STATUS_IDX 0x02 /* index pulse */
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#define STATUS_ERR 0x01 /* error */
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#define STATUS_ADMBSY 0x100 /* administratively busy (software) */
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#define REG_ERROR 1 /* error code */
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#define ERROR_BB 0x80 /* bad block */
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#define ERROR_ECC 0x40 /* bad ecc bytes */
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#define ERROR_ID 0x10 /* id not found */
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#define ERROR_AC 0x04 /* aborted command */
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#define ERROR_TK 0x02 /* track zero error */
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#define ERROR_DM 0x01 /* no data address mark */
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/* Write only registers */
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#define REG_COMMAND 7 /* command */
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#define CMD_IDLE 0x00 /* for w_command: drive idle */
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#define CMD_RECALIBRATE 0x10 /* recalibrate drive */
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#define CMD_READ 0x20 /* read data */
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#define CMD_READ_EXT 0x24 /* read data (LBA48 addressed) */
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#define CMD_READ_DMA_EXT 0x25 /* read data using DMA (w/ LBA48) */
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#define CMD_WRITE 0x30 /* write data */
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#define CMD_WRITE_EXT 0x34 /* write data (LBA48 addressed) */
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#define CMD_WRITE_DMA_EXT 0x35 /* write data using DMA (w/ LBA48) */
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#define CMD_READVERIFY 0x40 /* read verify */
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#define CMD_FORMAT 0x50 /* format track */
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#define CMD_SEEK 0x70 /* seek cylinder */
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#define CMD_DIAG 0x90 /* execute device diagnostics */
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#define CMD_SPECIFY 0x91 /* specify parameters */
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#define CMD_READ_DMA 0xC8 /* read data using DMA */
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#define CMD_WRITE_DMA 0xCA /* write data using DMA */
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#define CMD_FLUSH_CACHE 0xE7 /* flush the write cache */
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#define ATA_IDENTIFY 0xEC /* identify drive */
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/* #define REG_CTL 0x206 */ /* control register */
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#define REG_CTL 0 /* control register */
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#define CTL_NORETRY 0x80 /* disable access retry */
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#define CTL_NOECC 0x40 /* disable ecc retry */
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#define CTL_EIGHTHEADS 0x08 /* more than eight heads */
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#define CTL_RESET 0x04 /* reset controller */
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#define CTL_INTDISABLE 0x02 /* disable interrupts */
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#define REG_CTL_ALTSTAT 0 /* alternate status register */
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/* Identify words */
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#define ID_GENERAL 0x00 /* General configuration information */
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#define ID_GEN_NOT_ATA 0x8000 /* Not an ATA device */
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#define ID_CAPABILITIES 0x31 /* Capabilities (49)*/
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#define ID_CAP_LBA 0x0200 /* LBA supported */
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#define ID_CAP_DMA 0x0100 /* DMA supported */
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#define ID_FIELD_VALIDITY 0x35 /* Field Validity (53) */
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#define ID_FV_88 0x04 /* Word 88 is valid (UDMA) */
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#define ID_MULTIWORD_DMA 0x3f /* Multiword DMA (63) */
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#define ID_MWDMA_2_SEL 0x0400 /* Mode 2 is selected */
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#define ID_MWDMA_1_SEL 0x0200 /* Mode 1 is selected */
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#define ID_MWDMA_0_SEL 0x0100 /* Mode 0 is selected */
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#define ID_MWDMA_2_SUP 0x0004 /* Mode 2 is supported */
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#define ID_MWDMA_1_SUP 0x0002 /* Mode 1 is supported */
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#define ID_MWDMA_0_SUP 0x0001 /* Mode 0 is supported */
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#define ID_CSS 0x53 /* Command Sets Supported (83) */
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#define ID_CSS_LBA48 0x0400
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#define ID_ULTRA_DMA 0x58 /* Ultra DMA (88) */
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#define ID_UDMA_5_SEL 0x2000 /* Mode 5 is selected */
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#define ID_UDMA_4_SEL 0x1000 /* Mode 4 is selected */
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#define ID_UDMA_3_SEL 0x0800 /* Mode 3 is selected */
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#define ID_UDMA_2_SEL 0x0400 /* Mode 2 is selected */
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#define ID_UDMA_1_SEL 0x0200 /* Mode 1 is selected */
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#define ID_UDMA_0_SEL 0x0100 /* Mode 0 is selected */
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#define ID_UDMA_5_SUP 0x0020 /* Mode 5 is supported */
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#define ID_UDMA_4_SUP 0x0010 /* Mode 4 is supported */
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#define ID_UDMA_3_SUP 0x0008 /* Mode 3 is supported */
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#define ID_UDMA_2_SUP 0x0004 /* Mode 2 is supported */
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#define ID_UDMA_1_SUP 0x0002 /* Mode 1 is supported */
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#define ID_UDMA_0_SUP 0x0001 /* Mode 0 is supported */
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/* DMA registers */
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#define DMA_COMMAND 0 /* Command register */
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#define DMA_CMD_WRITE 0x08 /* PCI bus master writes */
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#define DMA_CMD_START 0x01 /* Start Bus Master */
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#define DMA_STATUS 2 /* Status register */
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#define DMA_ST_D1_DMACAP 0x40 /* Drive 1 is DMA capable */
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#define DMA_ST_D0_DMACAP 0x20 /* Drive 0 is DMA capable */
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#define DMA_ST_INT 0x04 /* Interrupt */
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#define DMA_ST_ERROR 0x02 /* Error */
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#define DMA_ST_BM_ACTIVE 0x01 /* Bus Master IDE Active */
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#define DMA_PRDTP 4 /* PRD Table Pointer */
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/* Check for the presence of LBA48 only on drives that are 'big'. */
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#define LBA48_CHECK_SIZE 0x0f000000
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#define LBA_MAX_SIZE 0x0fffffff /* Highest sector size for
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* regular LBA.
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*/
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#if ENABLE_ATAPI
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#define ERROR_SENSE 0xF0 /* sense key mask */
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#define SENSE_NONE 0x00 /* no sense key */
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#define SENSE_RECERR 0x10 /* recovered error */
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#define SENSE_NOTRDY 0x20 /* not ready */
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#define SENSE_MEDERR 0x30 /* medium error */
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#define SENSE_HRDERR 0x40 /* hardware error */
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#define SENSE_ILRQST 0x50 /* illegal request */
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#define SENSE_UATTN 0x60 /* unit attention */
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#define SENSE_DPROT 0x70 /* data protect */
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#define SENSE_ABRT 0xb0 /* aborted command */
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#define SENSE_MISCOM 0xe0 /* miscompare */
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#define ERROR_MCR 0x08 /* media change requested */
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#define ERROR_ABRT 0x04 /* aborted command */
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#define ERROR_EOM 0x02 /* end of media detected */
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#define ERROR_ILI 0x01 /* illegal length indication */
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#define REG_FEAT 1 /* features */
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#define FEAT_OVERLAP 0x02 /* overlap */
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#define FEAT_DMA 0x01 /* dma */
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#define REG_IRR 2 /* interrupt reason register */
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#define IRR_REL 0x04 /* release */
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#define IRR_IO 0x02 /* direction for xfer */
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#define IRR_COD 0x01 /* command or data */
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#define REG_SAMTAG 3
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#define REG_CNT_LO 4 /* low byte of cylinder number */
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#define REG_CNT_HI 5 /* high byte of cylinder number */
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#define REG_DRIVE 6 /* drive select */
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#endif
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#define REG_STATUS 7 /* status */
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#define STATUS_BSY 0x80 /* controller busy */
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#define STATUS_DRDY 0x40 /* drive ready */
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#define STATUS_DMADF 0x20 /* dma ready/drive fault */
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#define STATUS_SRVCDSC 0x10 /* service or dsc */
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#define STATUS_DRQ 0x08 /* data transfer request */
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#define STATUS_CORR 0x04 /* correctable error occurred */
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#define STATUS_CHECK 0x01 /* check error */
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#if ENABLE_ATAPI
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#define ATAPI_PACKETCMD 0xA0 /* packet command */
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#define ATAPI_IDENTIFY 0xA1 /* identify drive */
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#define SCSI_READ10 0x28 /* read from disk */
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#define SCSI_SENSE 0x03 /* sense request */
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#endif /* ATAPI */
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/* Interrupt request lines. */
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#define NO_IRQ 0 /* no IRQ set yet */
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#define ATAPI_PACKETSIZE 12
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#define SENSE_PACKETSIZE 18
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/* Error codes */
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#define ERR (-1) /* general error */
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#define ERR_BAD_SECTOR (-2) /* block marked bad detected */
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/* Some controllers don't interrupt, the clock will wake us up. */
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#define WAKEUP_SECS 32 /* drive may be out for 31 seconds max */
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#define WAKEUP_TICKS (WAKEUP_SECS*system_hz)
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/* Miscellaneous. */
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#define MAX_DRIVES 8
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#define COMPAT_DRIVES 4
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#if _WORD_SIZE > 2
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#define MAX_SECS 256 /* controller can transfer this many sectors */
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#else
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#define MAX_SECS 127 /* but not to a 16 bit process */
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#endif
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#define MAX_ERRORS 4 /* how often to try rd/wt before quitting */
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#define NR_MINORS (MAX_DRIVES * DEV_PER_DRIVE)
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#define SUB_PER_DRIVE (NR_PARTITIONS * NR_PARTITIONS)
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#define NR_SUBDEVS (MAX_DRIVES * SUB_PER_DRIVE)
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#define DELAY_USECS 1000 /* controller timeout in microseconds */
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#define DELAY_TICKS 1 /* controller timeout in ticks */
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#define DEF_TIMEOUT_USECS 5000000L /* controller timeout in microseconds */
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#define RECOVERY_USECS 500000 /* controller recovery time in microseconds */
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#define RECOVERY_TICKS 30 /* controller recovery time in ticks */
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#define INITIALIZED 0x01 /* drive is initialized */
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#define DEAF 0x02 /* controller must be reset */
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#define SMART 0x04 /* drive supports ATA commands */
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#if ENABLE_ATAPI
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#define ATAPI 0x08 /* it is an ATAPI device */
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#else
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#define ATAPI 0 /* don't bother with ATAPI; optimise out */
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#endif
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#define IDENTIFIED 0x10 /* w_identify done successfully */
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#define IGNORING 0x20 /* w_identify failed once */
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#define NO_DMA_VAR "ata_no_dma"
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/* BIOS parameter table layout. */
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#define bp_cylinders(t) (t[0] | (t[1] << 8))
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#define bp_heads(t) (t[2])
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#define bp_precomp(t) (t[5] | (t[6] << 8))
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#define bp_sectors(t) (t[14])
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