5efa92f754
There is not that much use for it on a single CPU, however, deadlock between kernel and system task can be delected. Or a runaway loop. If a kernel gets locked up the timer interrupts don't occure (as all interrupts are disabled in kernel mode). The only chance is to interrupt the kernel by a non-maskable interrupt. This patch generates NMIs using performance counters. It uses the most widely available performace counters. As the performance counters are highly model-specific this patch is not guaranteed to work on every machine. Unfortunately this is also true for KVM :-/ On the other hand adding this feature for other models is not extremely difficult and the framework makes it hopefully easy enough. Depending on the frequency of the CPU an NMI is generated at most about every 0.5s If the cpu's speed is less then 2Ghz it is generated at most every 1s. In general an NMI is generated much less often as the performance counter counts down only if the cpu is not idle. Therefore the overhead of this feature is fairly minimal even if the load is high. Uppon detecting that the kernel is locked up the kernel dumps the state of the kernel registers and panics. Local APIC must be enabled for the watchdog to work. The code is _always_ compiled in, however, it is only enabled if watchdog=<non-zero> is set in the boot monitor. One corner case is serial console debugging. As dumping a lot of stuff to the serial link may take a lot of time, the watchdog does not detect lockups during this time!!! as it would result in too many false positives. 10 nmi have to be handled before the lockup is detected. This means something between ~5s to 10s. Another corner case is that the watchdog is enabled only after the paging is enabled as it would be pure madness to try to get it right.
161 lines
4.5 KiB
C
161 lines
4.5 KiB
C
#ifndef __APIC_H__
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#define __APIC_H__
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#define APIC_ENABLE 0x100
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#define APIC_FOCUS_DISABLED (1 << 9)
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#define APIC_SIV 0xFF
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#define APIC_TDCR_2 0x00
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#define APIC_TDCR_4 0x01
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#define APIC_TDCR_8 0x02
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#define APIC_TDCR_16 0x03
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#define APIC_TDCR_32 0x08
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#define APIC_TDCR_64 0x09
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#define APIC_TDCR_128 0x0a
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#define APIC_TDCR_1 0x0b
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#define APIC_LVTT_VECTOR_MASK 0x000000FF
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#define APIC_LVTT_DS_PENDING (1 << 12)
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#define APIC_LVTT_MASK (1 << 16)
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#define APIC_LVTT_TM (1 << 17)
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#define APIC_LVT_IIPP_MASK 0x00002000
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#define APIC_LVT_IIPP_AH 0x00002000
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#define APIC_LVT_IIPP_AL 0x00000000
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#define IOAPIC_REGSEL 0x0
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#define IOAPIC_RW 0x10
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#define APIC_ICR_DM_MASK 0x00000700
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#define APIC_ICR_VECTOR APIC_LVTT_VECTOR_MASK
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#define APIC_ICR_DM_FIXED (0 << 8)
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#define APIC_ICR_DM_LOWEST_PRIORITY (1 << 8)
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#define APIC_ICR_DM_SMI (2 << 8)
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#define APIC_ICR_DM_RESERVED (3 << 8)
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#define APIC_ICR_DM_NMI (4 << 8)
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#define APIC_ICR_DM_INIT (5 << 8)
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#define APIC_ICR_DM_STARTUP (6 << 8)
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#define APIC_ICR_DM_EXTINT (7 << 8)
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#define APIC_ICR_DM_PHYSICAL (0 << 11)
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#define APIC_ICR_DM_LOGICAL (1 << 11)
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#define APIC_ICR_DELIVERY_PENDING (1 << 12)
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#define APIC_ICR_INT_POLARITY (1 << 13)
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#define APIC_ICR_LEVEL_ASSERT (1 << 14)
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#define APIC_ICR_LEVEL_DEASSERT (0 << 14)
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#define APIC_ICR_TRIGGER (1 << 15)
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#define APIC_ICR_INT_MASK (1 << 16)
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#define APIC_ICR_DEST_FIELD (0 << 18)
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#define APIC_ICR_DEST_SELF (1 << 18)
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#define APIC_ICR_DEST_ALL (2 << 18)
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#define APIC_ICR_DEST_ALL_BUT_SELF (3 << 18)
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#define LOCAL_APIC_DEF_ADDR 0xfee00000 /* default local apic address */
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#define IO_APIC_DEF_ADDR 0xfec00000 /* default i/o apic address */
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#define LAPIC_ID (lapic_addr + 0x020)
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#define LAPIC_VERSION (lapic_addr + 0x030)
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#define LAPIC_TPR (lapic_addr + 0x080)
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#define LAPIC_EOI (lapic_addr + 0x0b0)
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#define LAPIC_LDR (lapic_addr + 0x0d0)
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#define LAPIC_DFR (lapic_addr + 0x0e0)
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#define LAPIC_SIVR (lapic_addr + 0x0f0)
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#define LAPIC_ESR (lapic_addr + 0x280)
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#define LAPIC_ICR1 (lapic_addr + 0x300)
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#define LAPIC_ICR2 (lapic_addr + 0x310)
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#define LAPIC_LVTTR (lapic_addr + 0x320)
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#define LAPIC_LVTTMR (lapic_addr + 0x330)
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#define LAPIC_LVTPCR (lapic_addr + 0x340)
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#define LAPIC_LINT0 (lapic_addr + 0x350)
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#define LAPIC_LINT1 (lapic_addr + 0x360)
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#define LAPIC_LVTER (lapic_addr + 0x370)
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#define LAPIC_TIMER_ICR (lapic_addr + 0x380)
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#define LAPIC_TIMER_CCR (lapic_addr + 0x390)
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#define LAPIC_TIMER_DCR (lapic_addr + 0x3e0)
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#define IOAPIC_ID 0x0
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#define IOAPIC_VERSION 0x1
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#define IOAPIC_ARB 0x2
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#define IOAPIC_REDIR_TABLE 0x10
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#define APIC_TIMER_INT_VECTOR 0xfe
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#define APIC_SPURIOUS_INT_VECTOR 0xff
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#ifndef __ASSEMBLY__
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#include "../../kernel.h"
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EXTERN int ioapic_enabled;
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EXTERN u32_t lapic_addr;
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EXTERN u32_t lapic_eoi_addr;
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EXTERN u32_t lapic_taskpri_addr;
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EXTERN int bsp_lapic_id;
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#define MAX_NR_IOAPICS 32
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#define MAX_NR_BUSES 32
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#define MAX_NR_APICIDS 255
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#define MAX_NR_LCLINTS 2
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EXTERN u8_t apicid2cpuid[MAX_NR_APICIDS+1];
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EXTERN unsigned apic_imcrp;
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EXTERN unsigned nioapics;
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EXTERN unsigned nbuses;
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EXTERN unsigned nintrs;
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EXTERN unsigned nlints;
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EXTERN u32_t ioapic_id_mask[8];
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EXTERN u32_t lapic_id_mask[8];
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EXTERN u32_t lapic_addr_vaddr; /* we remember the virtual address here until we
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switch to paging */
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EXTERN u32_t lapic_addr;
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EXTERN u32_t lapic_eoi_addr;
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EXTERN u32_t lapic_taskpri_addr;
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_PROTOTYPE (void calc_bus_clock, (void));
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_PROTOTYPE (u32_t lapic_errstatus, (void));
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/*
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_PROTOTYPE (u32_t ioapic_read, (u32_t addr, u32_t offset));
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_PROTOTYPE (void ioapic_write, (u32_t addr, u32_t offset, u32_t data));
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_PROTOTYPE (void lapic_eoi, (void));
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*/
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_PROTOTYPE (void lapic_microsec_sleep, (unsigned count));
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_PROTOTYPE (void smp_ioapic_unmask, (void));
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_PROTOTYPE (void ioapic_disable_irqs, (u32_t irq));
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_PROTOTYPE (void ioapic_enable_irqs, (u32_t irq));
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_PROTOTYPE (u32_t ioapic_irqs_inuse, (void));
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_PROTOTYPE (void smp_recv_ipi, (int arg));
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_PROTOTYPE (void ioapic_config_pci_irq, (u32_t data));
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_PROTOTYPE (int lapic_enable, (void));
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_PROTOTYPE (void lapic_disable, (void));
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_PROTOTYPE (void ioapic_disable_all, (void));
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_PROTOTYPE (int ioapic_enable_all, (void));
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_PROTOTYPE(void apic_idt_init, (int reset));
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_PROTOTYPE(int apic_single_cpu_init, (void));
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_PROTOTYPE(void lapic_set_timer_periodic, (unsigned freq));
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_PROTOTYPE(void lapic_stop_timer, (void));
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#include <minix/cpufeature.h>
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#define cpu_feature_apic_on_chip() _cpufeature(_CPUF_I386_APIC_ON_CHIP)
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#define lapic_read(what) (*((u32_t *)((what))))
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#define lapic_write(what, data) do { \
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(*((u32_t *)((what)))) = data; \
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} while(0)
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#endif /* __ASSEMBLY__ */
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#endif /* __APIC_H__ */
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