166 lines
5.2 KiB
C
166 lines
5.2 KiB
C
/*
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** File: 3c503.c Dec. 20, 1996
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**
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** Author: Giovanni Falzoni <gfalzoni@inwind.it>
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**
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** Driver for the Etherlink II boards. Works in shared memory mode.
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** Programmed I/O could be used as well but would result in poor
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** performances. This file contains only the board specific code,
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** the rest is in 8390.c Code specific for ISA bus only
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*/
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#include <minix/drivers.h>
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#include <net/gen/ether.h>
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#include <net/gen/eth_io.h>
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#include "dp.h"
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#if (ENABLE_3C503 == 1)
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#include "8390.h"
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#include "3c503.h"
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/*
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** Name: void el2_init(dpeth_t *dep);
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** Function: Initalize hardware and data structures.
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*/
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static void el2_init(dpeth_t * dep)
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{
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int ix, irq;
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int sendq_nr;
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int cntr;
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/* Map the address PROM to lower I/O address range */
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cntr = inb_el2(dep, EL2_CNTR);
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outb_el2(dep, EL2_CNTR, cntr | ECNTR_SAPROM);
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/* Read station address from PROM */
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for (ix = EL2_EA0; ix <= EL2_EA5; ix += 1)
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dep->de_address.ea_addr[ix] = inb_el2(dep, ix);
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/* Map the 8390 back to lower I/O address range */
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outb_el2(dep, EL2_CNTR, cntr);
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/* Enable memory, but turn off interrupts until we are ready */
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outb_el2(dep, EL2_CFGR, ECFGR_IRQOFF);
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dep->de_data_port = dep->de_dp8390_port = dep->de_base_port;
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dep->de_prog_IO = FALSE; /* Programmed I/O not yet available */
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/* Check width of data bus */
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outb_el2(dep, DP_CR, CR_PS_P0 | CR_NO_DMA | CR_STP);
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outb_el2(dep, DP_DCR, 0);
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outb_el2(dep, DP_CR, CR_PS_P2 | CR_NO_DMA | CR_STP);
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dep->de_16bit = (inb_el2(dep, DP_DCR) & DCR_WTS) != 0;
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outb_el2(dep, DP_CR, CR_PS_P0 | CR_NO_DMA | CR_STP);
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/* Allocate one send buffer (1.5kb) per 8kb of on board memory. */
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/* Only 8kb of 3c503/16 boards are used to avoid specific routines */
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sendq_nr = dep->de_ramsize / 0x2000;
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if (sendq_nr < 1)
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sendq_nr = 1;
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else if (sendq_nr > SENDQ_NR)
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sendq_nr = SENDQ_NR;
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dep->de_sendq_nr = sendq_nr;
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for (ix = 0; ix < sendq_nr; ix++)
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dep->de_sendq[ix].sq_sendpage = (ix * SENDQ_PAGES) + EL2_SM_START_PG;
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dep->de_startpage = (ix * SENDQ_PAGES) + EL2_SM_START_PG;
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dep->de_stoppage = EL2_SM_STOP_PG;
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outb_el2(dep, EL2_STARTPG, dep->de_startpage);
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outb_el2(dep, EL2_STOPPG, dep->de_stoppage);
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/* Point the vector pointer registers somewhere ?harmless?. */
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outb_el2(dep, EL2_VP2, 0xFF); /* Point at the ROM restart location */
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outb_el2(dep, EL2_VP1, 0xFF); /* 0xFFFF:0000 (from original sources) */
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outb_el2(dep, EL2_VP0, 0x00); /* - What for protected mode? */
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/* Set interrupt level for 3c503 */
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irq = (dep->de_irq &= ~DEI_DEFAULT); /* Strip the default flag. */
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if (irq == 9) irq = 2;
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if (irq < 2 || irq > 5) panic("bad 3c503 irq configuration: %d", irq);
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outb_el2(dep, EL2_IDCFG, (0x04 << irq));
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outb_el2(dep, EL2_DRQCNT, 0x08); /* Set burst size to 8 */
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outb_el2(dep, EL2_DMAAH, EL2_SM_START_PG); /* Put start of TX */
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outb_el2(dep, EL2_DMAAL, 0x00); /* buffer in the GA DMA reg */
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outb_el2(dep, EL2_CFGR, ECFGR_NORM); /* Enable shared memory */
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ns_init(dep); /* Initialize DP controller */
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printf("%s: Etherlink II%s (%s) at %X:%d:%05lX - ",
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dep->de_name, dep->de_16bit ? "/16" : "", "3c503",
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dep->de_base_port, dep->de_irq,
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dep->de_linmem + dep->de_offset_page);
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for (ix = 0; ix < SA_ADDR_LEN; ix += 1)
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printf("%02X%c", dep->de_address.ea_addr[ix],
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ix < SA_ADDR_LEN - 1 ? ':' : '\n');
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return;
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}
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/*
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** Name: void el2_stop(dpeth_t *dep);
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** Function: Stops board by disabling interrupts.
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*/
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static void el2_stop(dpeth_t * dep)
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{
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outb_el2(dep, EL2_CFGR, ECFGR_IRQOFF);
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sys_irqdisable(&dep->de_hook); /* disable interrupts */
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return;
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}
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/*
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** Name: void el2_probe(dpeth_t *dep);
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** Function: Probe for the presence of an EtherLink II card.
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** Initialize memory addressing if card detected.
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*/
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int el2_probe(dpeth_t * dep)
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{
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int iobase, membase;
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int thin;
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/* Thin ethernet or AUI? */
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thin = (dep->de_linmem & 1) ? ECNTR_AUI : ECNTR_THIN;
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/* Location registers should have 1 bit set */
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if (!(iobase = inb_el2(dep, EL2_IOBASE))) return FALSE;
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if (!((membase = inb_el2(dep, EL2_MEMBASE)) & 0xF0)) return FALSE;
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if ((iobase & (iobase - 1)) || (membase & (membase - 1))) return FALSE;
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/* Resets board */
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outb_el2(dep, EL2_CNTR, ECNTR_RESET | thin);
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milli_delay(1);
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outb_el2(dep, EL2_CNTR, thin);
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milli_delay(5);
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/* Map the address PROM to lower I/O address range */
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outb_el2(dep, EL2_CNTR, ECNTR_SAPROM | thin);
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if (inb_el2(dep, EL2_EA0) != 0x02 || /* Etherlink II Station address */
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inb_el2(dep, EL2_EA1) != 0x60 || /* MUST be 02:60:8c:xx:xx:xx */
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inb_el2(dep, EL2_EA2) != 0x8C)
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return FALSE; /* No Etherlink board at this address */
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/* Map the 8390 back to lower I/O address range */
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outb_el2(dep, EL2_CNTR, thin);
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/* Setup shared memory addressing for 3c503 */
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dep->de_linmem = ((membase & 0xC0) ? EL2_BASE_0D8000 : EL2_BASE_0C8000) +
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((membase & 0xA0) ? (EL2_BASE_0CC000 - EL2_BASE_0C8000) : 0x0000);
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/* Shared memory starts at 0x2000 (8kb window) */
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dep->de_offset_page = (EL2_SM_START_PG * DP_PAGESIZE);
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dep->de_linmem -= dep->de_offset_page;
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dep->de_ramsize = (EL2_SM_STOP_PG - EL2_SM_START_PG) * DP_PAGESIZE;
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/* Board initialization and stop functions */
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dep->de_initf = el2_init;
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dep->de_stopf = el2_stop;
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return TRUE;
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}
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#endif /* ENABLE_3C503 */
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/** 3c503.c **/
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