315 lines
14 KiB
C
315 lines
14 KiB
C
#ifndef _AHCI_H
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#define _AHCI_H
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#include <minix/drivers.h>
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#define NR_PORTS 32 /* maximum number of ports */
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#define NR_CMDS 32 /* maximum number of queued commands */
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/* Time values that can be set with options. */
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#define SPINUP_TIMEOUT 5000 /* initial spin-up time (ms) */
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#define DEVICE_TIMEOUT 30000 /* time to wait for device (ms) */
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#define COMMAND_TIMEOUT 10000 /* time to wait for non-I/O cmd (ms) */
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#define TRANSFER_TIMEOUT 30000 /* time to wait for I/O cmd (ms) */
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#define FLUSH_TIMEOUT 60000 /* time to wait for flush cmd (ms) */
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/* Time values that are defined by the standards. */
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#define COMRESET_DELAY 1 /* time to assert port reset (ms) */
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#define RESET_DELAY 1000 /* maximum HBA reset time (ms) */
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#define PORTREG_DELAY 500 /* maximum port register update (ms) */
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/* Other hardcoded time values. */
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#define DEVICE_DELAY 100 /* time between device checks (ms) */
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/* Generic FIS layout. */
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#define ATA_FIS_TYPE 0 /* FIS Type */
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#define ATA_FIS_TYPE_H2D 0x27 /* Register - Host to Device */
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/* Register - Host to Device FIS layout. */
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#define ATA_H2D_SIZE 20 /* byte size of H2D FIS */
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#define ATA_H2D_FLAGS 1 /* C and PM Port */
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#define ATA_H2D_FLAGS_C 0x80 /* update command register */
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#define ATA_H2D_CMD 2 /* Command */
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#define ATA_CMD_READ_DMA_EXT 0x25 /* READ DMA EXT */
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#define ATA_CMD_WRITE_DMA_EXT 0x35 /* WRITE DMA EXT */
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#define ATA_CMD_READ_FPDMA_QUEUED 0x60 /* READ FPDMA QUEUED */
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#define ATA_CMD_WRITE_FPDMA_QUEUED 0x61 /* WRITE FPDMA QUEUED */
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#define ATA_CMD_WRITE_DMA_FUA_EXT 0x3D /* WRITE DMA FUA EXT */
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#define ATA_CMD_PACKET 0xA0 /* PACKET */
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#define ATA_CMD_IDENTIFY_PACKET 0xA1 /* IDENTIFY PACKET DEVICE */
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#define ATA_CMD_FLUSH_CACHE 0xE7 /* FLUSH CACHE */
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#define ATA_CMD_IDENTIFY 0xEC /* IDENTIFY DEVICE */
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#define ATA_CMD_SET_FEATURES 0xEF /* SET FEATURES */
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#define ATA_H2D_FEAT 3 /* Features */
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#define ATA_FEAT_PACKET_DMA 0x01 /* use DMA */
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#define ATA_FEAT_PACKET_DMADIR 0x03 /* DMA is inbound */
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#define ATA_H2D_LBA_LOW 4 /* LBA Low */
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#define ATA_H2D_LBA_MID 5 /* LBA Mid */
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#define ATA_H2D_LBA_HIGH 6 /* LBA High */
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#define ATA_H2D_DEV 7 /* Device */
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#define ATA_DEV_LBA 0x40 /* use LBA addressing */
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#define ATA_DEV_FUA 0x80 /* Force Unit Access (FPDMA) */
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#define ATA_H2D_LBA_LOW_EXP 8 /* LBA Low (exp) */
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#define ATA_H2D_LBA_MID_EXP 9 /* LBA Mid (exp) */
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#define ATA_H2D_LBA_HIGH_EXP 10 /* LBA High (exp) */
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#define ATA_H2D_FEAT_EXP 11 /* Features (exp) */
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#define ATA_H2D_SEC 12 /* Sector Count */
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#define ATA_SEC_TAG_SHIFT 3 /* NCQ command tag */
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#define ATA_H2D_SEC_EXP 13 /* Sector Count (exp) */
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#define ATA_H2D_CTL 15 /* Control */
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#define ATA_IS_FPDMA_CMD(c) \
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((c) == ATA_CMD_READ_FPDMA_QUEUED || \
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(c) == ATA_CMD_WRITE_FPDMA_QUEUED)
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/* ATA constants. */
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#define ATA_SECTOR_SIZE 512 /* default sector size */
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#define ATA_MAX_SECTORS 0x10000 /* max sectors per transfer */
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#define ATA_ID_SIZE (256 * sizeof(u16_t)) /* IDENTIFY result size */
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#define ATA_ID_GCAP 0 /* General capabililties */
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#define ATA_ID_GCAP_ATAPI_MASK 0xC000 /* ATAPI device mask */
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#define ATA_ID_GCAP_ATAPI 0x8000 /* ATAPI device */
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#define ATA_ID_GCAP_ATA_MASK 0x8000 /* ATA device mask */
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#define ATA_ID_GCAP_ATA 0x0000 /* ATA device */
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#define ATA_ID_GCAP_TYPE_MASK 0x1F00 /* ATAPI device type */
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#define ATA_ID_GCAP_TYPE_SHIFT 8 /* (one of ATAPI_TYPE_*) */
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#define ATA_ID_GCAP_REMOVABLE 0x0080 /* Removable media device */
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#define ATA_ID_GCAP_INCOMPLETE 0x0004 /* Incomplete response */
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#define ATA_ID_CAP 49 /* Capabilities */
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#define ATA_ID_CAP_DMA 0x0100 /* DMA supported (no DMADIR) */
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#define ATA_ID_CAP_LBA 0x0200 /* LBA supported */
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#define ATA_ID_DMADIR 62 /* DMADIR */
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#define ATA_ID_DMADIR_DMADIR 0x8000 /* DMADIR required */
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#define ATA_ID_DMADIR_DMA 0x0400 /* DMA supported (DMADIR) */
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#define ATA_ID_QDEPTH 75 /* NCQ queue depth */
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#define ATA_ID_QDEPTH_MASK 0x000F /* NCQ queue depth mask */
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#define ATA_ID_SATA_CAP 76 /* SATA capabilities */
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#define ATA_ID_SATA_CAP_NCQ 0x0100 /* NCQ support */
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#define ATA_ID_SUP0 82 /* Features supported (1/3) */
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#define ATA_ID_SUP0_WCACHE 0x0020 /* Write cache supported */
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#define ATA_ID_SUP1 83 /* Features supported (2/3) */
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#define ATA_ID_SUP1_VALID_MASK 0xC000 /* Word validity mask */
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#define ATA_ID_SUP1_VALID 0x4000 /* Word contents are valid */
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#define ATA_ID_SUP1_FLUSH 0x1000 /* FLUSH CACHE supported */
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#define ATA_ID_SUP1_LBA48 0x0400 /* 48-bit LBA supported */
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#define ATA_ID_ENA0 85 /* Features enabled (1/3) */
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#define ATA_ID_ENA0_WCACHE 0x0020 /* Write cache enabled */
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#define ATA_ID_ENA2 87 /* Features enabled (3/3) */
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#define ATA_ID_ENA2_VALID_MASK 0xC000 /* Word validity mask */
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#define ATA_ID_ENA2_VALID 0x4000 /* Word contents are valid */
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#define ATA_ID_ENA2_FUA 0x0040 /* Forced Unit Access sup. */
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#define ATA_ID_LBA0 100 /* Max. LBA48 address (LSW) */
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#define ATA_ID_LBA1 101 /* Max. LBA48 address */
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#define ATA_ID_LBA2 102 /* Max. LBA48 address */
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#define ATA_ID_LBA3 103 /* Max. LBA48 address (MSW) */
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#define ATA_ID_PLSS 106 /* Phys./logical sector size */
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#define ATA_ID_PLSS_VALID_MASK 0xC000 /* Word validity mask */
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#define ATA_ID_PLSS_VALID 0x4000 /* Word contents are valid */
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#define ATA_ID_PLSS_LLS 0x1000 /* Long logical sectors */
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#define ATA_ID_LSS0 118 /* Logical sector size (LSW) */
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#define ATA_ID_LSS1 119 /* Logical sector size (MSW) */
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#define ATA_SF_EN_WCACHE 0x02 /* Enable write cache */
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#define ATA_SF_DI_WCACHE 0x82 /* Disable write cache */
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/* ATAPI constants. */
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#define ATAPI_PACKET_SIZE 16 /* ATAPI packet size */
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#define ATAPI_TYPE_CDROM 5 /* CD-ROM device */
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#define ATAPI_CMD_TEST_UNIT 0x00 /* Test Unit Ready */
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#define ATAPI_CMD_REQUEST_SENSE 0x03 /* Request Sense */
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#define ATAPI_REQUEST_SENSE_LEN 18 /* result length */
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#define ATAPI_SENSE_UNIT_ATT 6 /* Unit Attention */
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#define ATAPI_CMD_START_STOP 0x1B /* Start/Stop Unit */
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#define ATAPI_START_STOP_EJECT 0x02 /* eject the medium */
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#define ATAPI_START_STOP_LOAD 0x03 /* load the medium */
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#define ATAPI_CMD_READ_CAPACITY 0x25 /* Read Capacity */
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#define ATAPI_READ_CAPACITY_LEN 8 /* result length */
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#define ATAPI_CMD_READ 0xA8 /* Read (12) */
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#define ATAPI_CMD_WRITE 0xAA /* Write (12) */
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/* Command List constants. */
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#define AHCI_CL_ENTRY_SIZE 32 /* Command List header size */
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#define AHCI_CL_ENTRY_DWORDS (AHCI_CL_ENTRY_SIZE / sizeof(u32_t))
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#define AHCI_CL_PRDTL_SHIFT 16 /* PRD Table Length */
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#define AHCI_CL_PREFETCHABLE (1L << 7) /* Prefetchable */
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#define AHCI_CL_WRITE (1L << 6) /* Write */
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#define AHCI_CL_ATAPI (1L << 5) /* ATAPI */
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#define AHCI_CL_CFL_SHIFT 0 /* Command FIS Length */
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/* Command Table offsets. */
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#define AHCI_CT_PACKET_OFF 0x40 /* CT offset to ATAPI packet */
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#define AHCI_CT_PRDT_OFF 0x80 /* CT offset to PRD table */
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/* Host Bus Adapter (HBA) constants. */
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#define AHCI_HBA_CAP 0 /* Host Capabilities */
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#define AHCI_HBA_CAP_SNCQ (1L << 30) /* Native Cmd Queuing */
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#define AHCI_HBA_CAP_SCLO (1L << 24) /* Cmd List Override */
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#define AHCI_HBA_CAP_NCS_SHIFT 8 /* Nr of Cmd Slots */
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#define AHCI_HBA_CAP_NCS_MASK 0x1FL
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#define AHCI_HBA_CAP_NP_SHIFT 0 /* Nr of Ports */
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#define AHCI_HBA_CAP_NP_MASK 0x1FL
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#define AHCI_HBA_GHC 1 /* Global Host Control */
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#define AHCI_HBA_GHC_AE (1L << 31) /* AHCI Enable */
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#define AHCI_HBA_GHC_IE (1L << 1) /* Interrupt Enable */
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#define AHCI_HBA_GHC_HR (1L << 0) /* HBA Reset */
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#define AHCI_HBA_IS 2 /* Interrupt Status */
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#define AHCI_HBA_PI 3 /* Ports Implemented */
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#define AHCI_HBA_VS 4 /* Version */
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#define AHCI_HBA_CAP2 9 /* Host Capabilities Extended */
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/* Port constants. */
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#define AHCI_PORT_CLB 0 /* Command List Base */
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#define AHCI_PORT_CLBU 1 /* Command List Base, Upper 32 bits */
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#define AHCI_PORT_FB 2 /* FIS Base */
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#define AHCI_PORT_FBU 3 /* FIS Base, Upper 32 bits */
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#define AHCI_PORT_IS 4 /* Interrupt Status */
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#define AHCI_PORT_IS_TFES (1L << 30) /* Task File Error */
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#define AHCI_PORT_IS_HBFS (1L << 29) /* Host Bus Fatal */
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#define AHCI_PORT_IS_HBDS (1L << 28) /* Host Bus Data */
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#define AHCI_PORT_IS_IFS (1L << 27) /* Interface Fatal */
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#define AHCI_PORT_IS_PRCS (1L << 22) /* PhyRdy Change */
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#define AHCI_PORT_IS_PCS (1L << 6) /* Port Conn Change */
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#define AHCI_PORT_IS_SDBS (1L << 3) /* Set Dev Bits FIS */
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#define AHCI_PORT_IS_PSS (1L << 1) /* PIO Setup FIS */
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#define AHCI_PORT_IS_DHRS (1L << 0) /* D2H Register FIS */
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#define AHCI_PORT_IS_RESTART \
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(AHCI_PORT_IS_TFES | AHCI_PORT_IS_HBFS | AHCI_PORT_IS_HBDS | \
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AHCI_PORT_IS_IFS)
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#define AHCI_PORT_IS_MASK \
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(AHCI_PORT_IS_RESTART | AHCI_PORT_IS_PRCS | AHCI_PORT_IS_DHRS | \
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AHCI_PORT_IS_PSS | AHCI_PORT_IS_SDBS)
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#define AHCI_PORT_IE 5 /* Interrupt Enable */
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#define AHCI_PORT_IE_MASK AHCI_PORT_IS_MASK
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#define AHCI_PORT_IE_PRCE AHCI_PORT_IS_PRCS
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#define AHCI_PORT_IE_PCE AHCI_PORT_IS_PCS
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#define AHCI_PORT_IE_NONE 0L
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#define AHCI_PORT_CMD 6 /* Command and Status */
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#define AHCI_PORT_CMD_CR (1L << 15) /* Cmd List Running */
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#define AHCI_PORT_CMD_FR (1L << 14) /* FIS Recv Running */
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#define AHCI_PORT_CMD_FRE (1L << 4) /* FIS Recv Enabled */
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#define AHCI_PORT_CMD_CLO (1L << 3) /* Cmd List Override */
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#define AHCI_PORT_CMD_SUD (1L << 1) /* Spin-Up Device */
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#define AHCI_PORT_CMD_ST (1L << 0) /* Start */
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#define AHCI_PORT_TFD 8 /* Task File Data */
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#define AHCI_PORT_TFD_STS_BSY (1L << 7) /* Busy */
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#define AHCI_PORT_TFD_STS_DF (1L << 5) /* Device Fault */
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#define AHCI_PORT_TFD_STS_DRQ (1L << 3) /* Data Xfer Req'd */
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#define AHCI_PORT_TFD_STS_ERR (1L << 0) /* Error */
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#define AHCI_PORT_TFD_STS_INIT 0x7F /* Initial state */
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#define AHCI_PORT_SIG 9 /* Signature */
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#define ATA_SIG_ATA 0x00000101L /* ATA interface */
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#define ATA_SIG_ATAPI 0xEB140101L /* ATAPI interface */
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#define AHCI_PORT_SSTS 10 /* Serial ATA Status */
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#define AHCI_PORT_SSTS_DET_MASK 0x00000007L /* Detection Mask */
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#define AHCI_PORT_SSTS_DET_DET 0x00000001L /* Device Detected */
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#define AHCI_PORT_SSTS_DET_PHY 0x00000003L /* PHY Comm Establ */
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#define AHCI_PORT_SCTL 11 /* Serial ATA Control */
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#define AHCI_PORT_SCTL_DET_INIT 0x00000001L /* Perform Init Seq */
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#define AHCI_PORT_SCTL_DET_NONE 0x00000000L /* No Action Req'd */
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#define AHCI_PORT_SERR 12 /* Serial ATA Error */
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#define AHCI_PORT_SERR_DIAG_X (1L << 26) /* Exchanged */
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#define AHCI_PORT_SERR_DIAG_N (1L << 16) /* PhyRdy Change */
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#define AHCI_PORT_SACT 13 /* Serial ATA Active */
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#define AHCI_PORT_CI 14 /* Command Issue */
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/* Number of Physical Region Descriptors (PRDs). Must be at least NR_IOREQS+2,
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* and at most 1024. There is currently no reason to use more than the minimum.
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*/
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#define NR_PRDS (NR_IOREQS + 2)
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/* Various size constants. */
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#define AHCI_MEM_BASE_SIZE 0x100 /* memory-mapped base region size */
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#define AHCI_MEM_PORT_SIZE 0x80 /* memory-mapped port region size */
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#define AHCI_FIS_SIZE 256 /* size of FIS receive buffer */
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#define AHCI_CL_SIZE 1024 /* size of command list buffer */
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#define AHCI_TMP_SIZE ATA_ID_SIZE /* size of temporary storage buffer */
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#define AHCI_TMP_ALIGN 2 /* required alignment for temp buf */
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#define AHCI_CT_SIZE (128 + NR_PRDS * sizeof(u32_t) * 4)
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/* size of command table buffer */
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#define AHCI_CT_ALIGN 128 /* required alignment for CT buffer */
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#define MAX_PRD_BYTES (1L << 22) /* maximum number of bytes per PRD */
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#define MAX_TRANSFER MAX_PRD_BYTES /* maximum size of a single transfer */
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/* Command Frame Information Structure (FIS). For internal use only;
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* the contents of this structure are later converted to an actual FIS.
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*/
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typedef struct {
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u8_t cf_cmd; /* Command */
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u8_t cf_feat; /* Features */
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u32_t cf_lba; /* LBA (24-bit) */
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u8_t cf_dev; /* Device */
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u32_t cf_lba_exp; /* LBA (exp) (24-bit) */
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u8_t cf_feat_exp; /* Features (exp) */
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u8_t cf_sec; /* Sector Count */
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u8_t cf_sec_exp; /* Sector Count (exp) */
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u8_t cf_ctl; /* Control */
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} cmd_fis_t;
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/* Physical Region Descriptor (PRD). For internal and sys_vumap() use only;
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* the contents of this structure are later converted to an actual PRD.
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*/
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typedef struct vumap_phys prd_t;
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/* These are from at_wini, as this driver is a drop-in replacement for at_wini.
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* Practically speaking this is already the upper limit with 256 minor device
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* numbers per driver, even though it means we can only ever expose 8 devices
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* out of potentially 32.
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*/
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#define MAX_DRIVES 8
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#define NR_MINORS (MAX_DRIVES * DEV_PER_DRIVE)
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#define NR_SUBDEVS (MAX_DRIVES * SUB_PER_DRIVE)
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/* Port states. */
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enum {
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STATE_NO_PORT, /* this port is not present */
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STATE_SPIN_UP, /* waiting for device or timeout after reset */
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STATE_NO_DEV, /* no device has been detected on this port */
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STATE_WAIT_DEV, /* waiting for functioning device to appear */
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STATE_WAIT_ID, /* waiting for device identification */
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STATE_BAD_DEV, /* an unusable device has been detected */
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STATE_GOOD_DEV /* a usable device has been detected */
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};
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/* Command results. */
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enum {
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RESULT_FAILURE,
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RESULT_SUCCESS
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};
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/* Port flags. */
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#define FLAG_ATAPI 0x00000001 /* is this an ATAPI device? */
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#define FLAG_HAS_MEDIUM 0x00000002 /* is a medium present? */
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#define FLAG_USE_DMADIR 0x00000004 /* use ATAPI DMADIR flag? */
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#define FLAG_READONLY 0x00000008 /* is the device read-only? */
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#define FLAG_BUSY 0x00000010 /* is an operation ongoing? */
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#define FLAG_FAILURE 0x00000020 /* did the operation fail? */
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#define FLAG_BARRIER 0x00000040 /* no access until unset */
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#define FLAG_HAS_WCACHE 0x00000080 /* is a write cache present? */
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#define FLAG_HAS_FLUSH 0x00000100 /* is FLUSH CACHE supported? */
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#define FLAG_SUSPENDED 0x00000200 /* is the thread suspended? */
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#define FLAG_HAS_FUA 0x00000400 /* is WRITE DMA FUA EX sup.? */
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#define FLAG_HAS_NCQ 0x00000800 /* is NCQ supported? */
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#define FLAG_NCQ_MODE 0x00001000 /* issuing NCQ commands? */
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/* Mapping between devices and ports. */
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#define NO_PORT -1 /* this device maps to no port */
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#define NO_DEVICE -1 /* this port maps to no device */
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/* Output verbosity levels. */
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enum {
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V_NONE, /* no output at all; keep silent */
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V_ERR, /* important error information only (the default) */
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V_INFO, /* general information about the driver and devices */
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V_DEV, /* device details, to help with detection problems */
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V_REQ /* detailed information about requests */
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};
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#endif /* _AHCI_H */
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