168 lines
4 KiB
C
168 lines
4 KiB
C
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#include "kernel/kernel.h"
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#include <unistd.h>
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#include <ctype.h>
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#include <string.h>
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#include <machine/cmos.h>
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#include <machine/bios.h>
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#include <machine/cpu.h>
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#include <minix/portio.h>
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#include <minix/cpufeature.h>
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#include <assert.h>
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#include <signal.h>
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#include <machine/vm.h>
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#include <minix/u64.h>
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#include "archconst.h"
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#include "arch_proto.h"
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#include "serial.h"
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#include "oxpcie.h"
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#include "direct_utils.h"
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#include <machine/multiboot.h>
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#define KBCMDP 4 /* kbd controller port (O) */
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#define KBC_PULSE0 0xfe /* pulse output bit 0 */
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#define IO_KBD 0x060 /* 8042 Keyboard */
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int cpu_has_tsc;
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void
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reset(void)
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{
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uint8_t b;
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/*
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* The keyboard controller has 4 random output pins, one of which is
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* connected to the RESET pin on the CPU in many PCs. We tell the
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* keyboard controller to pulse this line a couple of times.
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*/
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outb(IO_KBD + KBCMDP, KBC_PULSE0);
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busy_delay_ms(100);
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outb(IO_KBD + KBCMDP, KBC_PULSE0);
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busy_delay_ms(100);
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/*
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* Attempt to force a reset via the Reset Control register at
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* I/O port 0xcf9. Bit 2 forces a system reset when it
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* transitions from 0 to 1. Bit 1 selects the type of reset
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* to attempt: 0 selects a "soft" reset, and 1 selects a
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* "hard" reset. We try a "hard" reset. The first write sets
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* bit 1 to select a "hard" reset and clears bit 2. The
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* second write forces a 0 -> 1 transition in bit 2 to trigger
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* a reset.
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*/
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outb(0xcf9, 0x2);
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outb(0xcf9, 0x6);
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busy_delay_ms(500); /* wait 0.5 sec to see if that did it */
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/*
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* Attempt to force a reset via the Fast A20 and Init register
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* at I/O port 0x92. Bit 1 serves as an alternate A20 gate.
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* Bit 0 asserts INIT# when set to 1. We are careful to only
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* preserve bit 1 while setting bit 0. We also must clear bit
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* 0 before setting it if it isn't already clear.
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*/
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b = inb(0x92);
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if (b != 0xff) {
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if ((b & 0x1) != 0)
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outb(0x92, b & 0xfe);
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outb(0x92, b | 0x1);
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busy_delay_ms(500); /* wait 0.5 sec to see if that did it */
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}
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/* Triple fault */
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x86_triplefault();
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/* Give up on resetting */
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while(1) {
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;
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}
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}
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void
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poweroff(void)
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{
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const char *shutdown_str;
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/* Bochs/QEMU poweroff */
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shutdown_str = "Shutdown";
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while (*shutdown_str) outb(0x8900, *(shutdown_str++));
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/* fallback option: reset */
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reset();
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}
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__dead void arch_shutdown(int how)
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{
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unsigned char unused_ch;
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/* Mask all interrupts, including the clock. */
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outb( INT_CTLMASK, ~0);
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/* Empty buffer */
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while(direct_read_char(&unused_ch))
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;
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if(kinfo.minix_panicing) {
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/* Printing is done synchronously over serial. */
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if (kinfo.do_serial_debug)
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reset();
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/* Print accumulated diagnostics buffer and reset. */
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direct_cls();
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direct_print("Minix panic. System diagnostics buffer:\n\n");
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direct_print(kmess.kmess_buf);
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direct_print("\nSystem has panicked, press any key to reboot");
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while (!direct_read_char(&unused_ch))
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;
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reset();
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}
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switch (how) {
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case RBT_HALT:
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/* Stop */
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for (; ; ) halt_cpu();
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NOT_REACHABLE;
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case RBT_POWEROFF:
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/* Power off if possible, reset otherwise */
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poweroff();
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NOT_REACHABLE;
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default:
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case RBT_DEFAULT:
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case RBT_REBOOT:
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case RBT_RESET:
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/* Reset the system by forcing a processor shutdown.
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* First stop the BIOS memory test by setting a soft
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* reset flag.
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*/
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reset();
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NOT_REACHABLE;
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}
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NOT_REACHABLE;
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}
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#ifdef DEBUG_SERIAL
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void ser_putc(char c)
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{
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int i;
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int lsr, thr;
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#if CONFIG_OXPCIE
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oxpcie_putc(c);
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#else
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lsr= COM1_LSR;
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thr= COM1_THR;
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for (i= 0; i<100000; i++)
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{
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if (inb( lsr) & LSR_THRE)
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break;
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}
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outb( thr, c);
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#endif
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}
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#endif
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