84d9c625bf
- Fix for possible unset uid/gid in toproto
- Fix for default mtree style
- Update libelf
- Importing libexecinfo
- Resynchronize GCC, mpc, gmp, mpfr
- build.sh: Replace params with show-params.
This has been done as the make target has been renamed in the same
way, while a new target named params has been added. This new
target generates a file containing all the parameters, instead of
printing it on the console.
- Update test48 with new etc/services (Fix by Ben Gras <ben@minix3.org)
get getservbyport() out of the inner loop
Change-Id: Ie6ad5226fa2621ff9f0dee8782ea48f9443d2091
81 lines
2.3 KiB
C
81 lines
2.3 KiB
C
/* $NetBSD: intrdefs.h,v 1.19 2013/12/01 01:05:16 christos Exp $ */
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#ifndef _X86_INTRDEFS_H_
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#define _X86_INTRDEFS_H_
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/* Interrupt priority levels. */
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#define IPL_NONE 0x0 /* nothing */
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#define IPL_PREEMPT 0x1 /* fake, to prevent recursive preemptions */
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#define IPL_SOFTCLOCK 0x2 /* timeouts */
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#define IPL_SOFTBIO 0x3 /* block I/O passdown */
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#define IPL_SOFTNET 0x4 /* protocol stacks */
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#define IPL_SOFTSERIAL 0x5 /* serial passdown */
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#define IPL_VM 0x6 /* low I/O, memory allocation */
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#define IPL_SCHED 0x7 /* medium I/O, scheduler, clock */
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#define IPL_HIGH 0x8 /* high I/O, statclock, IPIs */
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#define NIPL 9
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/* Interrupt sharing types. */
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#define IST_NONE 0 /* none */
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#define IST_PULSE 1 /* pulsed */
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#define IST_EDGE 2 /* edge-triggered */
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#define IST_LEVEL 3 /* level-triggered */
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/*
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* Local APIC masks and software interrupt masks, in order
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* of priority. Must not conflict with SIR_* below.
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*/
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#define LIR_IPI 31
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#define LIR_TIMER 30
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/*
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* XXX These should be lowest numbered, but right now would
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* conflict with the legacy IRQs. Their current position
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* means that soft interrupt take priority over hardware
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* interrupts when lowering the priority level!
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*/
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#define SIR_SERIAL 29
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#define SIR_NET 28
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#define SIR_BIO 27
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#define SIR_CLOCK 26
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#define SIR_PREEMPT 25
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/*
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* Maximum # of interrupt sources per CPU. 32 to fit in one word.
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* ioapics can theoretically produce more, but it's not likely to
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* happen. For multiple ioapics, things can be routed to different
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* CPUs.
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*/
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#define MAX_INTR_SOURCES 32
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#define NUM_LEGACY_IRQS 16
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/*
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* Low and high boundaries between which interrupt gates will
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* be allocated in the IDT.
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*/
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#define IDT_INTR_LOW (0x20 + NUM_LEGACY_IRQS)
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#define IDT_INTR_HIGH 0xef
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#ifndef XEN
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#define X86_IPI_HALT 0x00000001
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#define X86_IPI_MICROSET 0x00000002
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#define X86_IPI__UNUSED1 0x00000004
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#define X86_IPI_SYNCH_FPU 0x00000008
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#define X86_IPI_MTRR 0x00000010
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#define X86_IPI_GDT 0x00000020
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#define X86_IPI_XCALL 0x00000040
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#define X86_IPI_ACPI_CPU_SLEEP 0x00000080
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#define X86_IPI_KPREEMPT 0x00000100
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#define X86_NIPI 9
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#define X86_IPI_NAMES { "halt IPI", "timeset IPI", "unused", \
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"FPU synch IPI", "MTRR update IPI", \
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"GDT update IPI", "xcall IPI", \
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"ACPI CPU sleep IPI", "kpreempt IPI" }
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#endif /* XEN */
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#define IREENT_MAGIC 0x18041969
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#endif /* _X86_INTRDEFS_H_ */
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