On the BeagleBoard-xM, the RTC is located on the Power Management IC (PMIC). To keep things consistent, access to the PMIC's RTC is done through the readclock driver. The readclock driver forwards the request on to the TPS65950 driver which does the work of manipulating the registers on the chip. Change-Id: I53cefbb59c5a9ab87fab90df3cc1a75a6e430f58
415 lines
12 KiB
C
415 lines
12 KiB
C
#include <minix/syslib.h>
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#include <minix/drvlib.h>
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#include <minix/log.h>
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#include <minix/mmio.h>
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#include <minix/clkconf.h>
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#include <minix/sysutil.h>
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#include <sys/mman.h>
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#include <sys/types.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <stdarg.h>
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#include <string.h>
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#include <errno.h>
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#include <assert.h>
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#include <time.h>
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#include "omap_rtc.h"
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#include "readclock.h"
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/* defines the set of register */
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typedef struct omap_rtc_registers
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{
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vir_bytes RTC_SS_SECONDS_REG;
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vir_bytes RTC_SS_MINUTES_REG;
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vir_bytes RTC_SS_HOURS_REG;
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vir_bytes RTC_SS_DAYS_REG;
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vir_bytes RTC_SS_MONTHS_REG;
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vir_bytes RTC_SS_YEARS_REG;
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vir_bytes RTC_SS_WEEKS_REG;
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vir_bytes RTC_SS_ALARM_SECONDS_REG;
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vir_bytes RTC_SS_ALARM_MINUTES_REG;
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vir_bytes RTC_SS_ALARM_HOURS_REG;
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vir_bytes RTC_SS_ALARM_DAYS_REG;
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vir_bytes RTC_SS_ALARM_MONTHS_REG;
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vir_bytes RTC_SS_ALARM_YEARS_REG;
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vir_bytes RTC_SS_RTC_CTRL_REG;
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vir_bytes RTC_SS_RTC_STATUS_REG;
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vir_bytes RTC_SS_RTC_INTERRUPTS_REG;
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vir_bytes RTC_SS_RTC_COMP_LSB_REG;
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vir_bytes RTC_SS_RTC_COMP_MSB_REG;
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vir_bytes RTC_SS_RTC_OSC_REG;
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vir_bytes RTC_SS_RTC_SCRATCH0_REG;
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vir_bytes RTC_SS_RTC_SCRATCH1_REG;
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vir_bytes RTC_SS_RTC_SCRATCH2_REG;
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vir_bytes RTC_SS_KICK0R;
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vir_bytes RTC_SS_KICK1R;
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vir_bytes RTC_SS_RTC_REVISION;
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vir_bytes RTC_SS_RTC_SYSCONFIG;
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vir_bytes RTC_SS_RTC_IRQWAKEEN;
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vir_bytes RTC_SS_ALARM2_SECONDS_REG;
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vir_bytes RTC_SS_ALARM2_MINUTES_REG;
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vir_bytes RTC_SS_ALARM2_HOURS_REG;
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vir_bytes RTC_SS_ALARM2_DAYS_REG;
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vir_bytes RTC_SS_ALARM2_MONTHS_REG;
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vir_bytes RTC_SS_ALARM2_YEARS_REG;
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vir_bytes RTC_SS_RTC_PMIC;
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vir_bytes RTC_SS_RTC_DEBOUNCE;
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} omap_rtc_registers_t;
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typedef struct omap_rtc_clock
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{
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enum rtc_clock_type
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{ am335x } clock_type;
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phys_bytes mr_base;
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phys_bytes mr_size;
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vir_bytes mapped_addr;
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omap_rtc_registers_t *regs;
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} omap_rtc_clock_t;
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/* Define the registers for each chip */
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static omap_rtc_registers_t am335x_rtc_regs = {
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.RTC_SS_SECONDS_REG = AM335X_RTC_SS_SECONDS_REG,
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.RTC_SS_MINUTES_REG = AM335X_RTC_SS_MINUTES_REG,
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.RTC_SS_HOURS_REG = AM335X_RTC_SS_HOURS_REG,
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.RTC_SS_DAYS_REG = AM335X_RTC_SS_DAYS_REG,
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.RTC_SS_MONTHS_REG = AM335X_RTC_SS_MONTHS_REG,
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.RTC_SS_YEARS_REG = AM335X_RTC_SS_YEARS_REG,
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.RTC_SS_WEEKS_REG = AM335X_RTC_SS_WEEKS_REG,
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.RTC_SS_ALARM_SECONDS_REG = AM335X_RTC_SS_ALARM_SECONDS_REG,
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.RTC_SS_ALARM_MINUTES_REG = AM335X_RTC_SS_ALARM_MINUTES_REG,
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.RTC_SS_ALARM_HOURS_REG = AM335X_RTC_SS_ALARM_HOURS_REG,
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.RTC_SS_ALARM_DAYS_REG = AM335X_RTC_SS_ALARM_DAYS_REG,
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.RTC_SS_ALARM_MONTHS_REG = AM335X_RTC_SS_ALARM_MONTHS_REG,
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.RTC_SS_ALARM_YEARS_REG = AM335X_RTC_SS_ALARM_YEARS_REG,
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.RTC_SS_RTC_CTRL_REG = AM335X_RTC_SS_RTC_CTRL_REG,
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.RTC_SS_RTC_STATUS_REG = AM335X_RTC_SS_RTC_STATUS_REG,
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.RTC_SS_RTC_INTERRUPTS_REG = AM335X_RTC_SS_RTC_INTERRUPTS_REG,
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.RTC_SS_RTC_COMP_LSB_REG = AM335X_RTC_SS_RTC_COMP_LSB_REG,
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.RTC_SS_RTC_COMP_MSB_REG = AM335X_RTC_SS_RTC_COMP_MSB_REG,
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.RTC_SS_RTC_OSC_REG = AM335X_RTC_SS_RTC_OSC_REG,
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.RTC_SS_RTC_SCRATCH0_REG = AM335X_RTC_SS_RTC_SCRATCH0_REG,
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.RTC_SS_RTC_SCRATCH1_REG = AM335X_RTC_SS_RTC_SCRATCH1_REG,
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.RTC_SS_RTC_SCRATCH2_REG = AM335X_RTC_SS_RTC_SCRATCH2_REG,
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.RTC_SS_KICK0R = AM335X_RTC_SS_KICK0R,
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.RTC_SS_KICK1R = AM335X_RTC_SS_KICK1R,
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.RTC_SS_RTC_REVISION = AM335X_RTC_SS_RTC_REVISION,
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.RTC_SS_RTC_SYSCONFIG = AM335X_RTC_SS_RTC_SYSCONFIG,
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.RTC_SS_RTC_IRQWAKEEN = AM335X_RTC_SS_RTC_IRQWAKEEN,
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.RTC_SS_ALARM2_SECONDS_REG = AM335X_RTC_SS_ALARM2_SECONDS_REG,
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.RTC_SS_ALARM2_MINUTES_REG = AM335X_RTC_SS_ALARM2_MINUTES_REG,
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.RTC_SS_ALARM2_HOURS_REG = AM335X_RTC_SS_ALARM2_HOURS_REG,
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.RTC_SS_ALARM2_DAYS_REG = AM335X_RTC_SS_ALARM2_DAYS_REG,
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.RTC_SS_ALARM2_MONTHS_REG = AM335X_RTC_SS_ALARM2_MONTHS_REG,
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.RTC_SS_ALARM2_YEARS_REG = AM335X_RTC_SS_ALARM2_YEARS_REG,
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.RTC_SS_RTC_PMIC = AM335X_RTC_SS_RTC_PMIC,
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.RTC_SS_RTC_DEBOUNCE = AM335X_RTC_SS_RTC_DEBOUNCE
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};
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static omap_rtc_clock_t rtc = {
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am335x, AM335X_RTC_SS_BASE, AM335X_RTC_SS_SIZE, 0, &am335x_rtc_regs
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};
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/* used for logging */
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static struct log log = {
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.name = "omap_rtc",
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.log_level = LEVEL_INFO,
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.log_func = default_log
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};
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static u32_t use_count = 0;
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static u32_t pwr_off_in_progress = 0;
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static void omap_rtc_unlock(void);
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static void omap_rtc_lock(void);
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static int omap_rtc_clkconf(void);
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/* Helper Functions for Register Access */
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#define reg_read(a) (*(volatile uint32_t *)(rtc.mapped_addr + a))
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#define reg_write(a,v) (*(volatile uint32_t *)(rtc.mapped_addr + a) = (v))
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#define reg_set_bit(a,v) reg_write((a), reg_read((a)) | (1<<v))
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#define reg_clear_bit(a,v) reg_write((a), reg_read((a)) & ~(1<<v))
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#define RTC_IS_BUSY (reg_read(rtc.regs->RTC_SS_RTC_STATUS_REG) & (1<<RTC_BUSY_BIT))
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/* When the RTC is running, writes should not happen when the RTC is busy.
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* This macro waits until the RTC is free before doing the write.
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*/
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#define safe_reg_write(a,v) do { while (RTC_IS_BUSY) {micro_delay(1);} reg_write((a),(v)); } while (0)
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#define safe_reg_set_bit(a,v) safe_reg_write((a), reg_read((a)) | (1<<v))
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#define safe_reg_clear_bit(a,v) safe_reg_write((a), reg_read((a)) & ~(1<<v))
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static void
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omap_rtc_unlock(void)
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{
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/* Specific bit patterns need to be written to specific registers in a
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* specific order to enable writing to RTC_SS registers.
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*/
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reg_write(rtc.regs->RTC_SS_KICK0R, AM335X_RTC_SS_KICK0R_UNLOCK_MASK);
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reg_write(rtc.regs->RTC_SS_KICK1R, AM335X_RTC_SS_KICK1R_UNLOCK_MASK);
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}
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static void
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omap_rtc_lock(void)
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{
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/* Write garbage to the KICK registers to enable write protect. */
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reg_write(rtc.regs->RTC_SS_KICK0R, AM335X_RTC_SS_KICK0R_LOCK_MASK);
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reg_write(rtc.regs->RTC_SS_KICK1R, AM335X_RTC_SS_KICK1R_LOCK_MASK);
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}
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static int
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omap_rtc_clkconf(void)
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{
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int r;
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/* Configure the clocks need to run the RTC */
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r = clkconf_init();
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if (r != OK) {
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return r;
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}
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r = clkconf_set(CM_RTC_RTC_CLKCTRL, 0xffffffff,
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CM_RTC_RTC_CLKCTRL_MASK);
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if (r != OK) {
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return r;
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}
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r = clkconf_set(CM_RTC_CLKSTCTRL, 0xffffffff, CM_RTC_CLKSTCTRL_MASK);
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if (r != OK) {
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return r;
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}
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r = clkconf_release();
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if (r != OK) {
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return r;
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}
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return OK;
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}
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int
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omap_rtc_init(void)
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{
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int r;
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int rtc_rev, major, minor;
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struct minix_mem_range mr;
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#ifndef AM335X
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/* Only the am335x (BeagleBone & BeagleBone Black) is supported ATM.
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* The dm37xx (BeagleBoard-xM) doesn't have a real time clock
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* built-in. Instead, it uses the RTC on the PMIC. A driver for
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* the BeagleBoard-xM's PMIC still needs to be developed.
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*/
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log_warn(&log, "unsupported processor\n");
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return ENOSYS;
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#endif /* !AM335X */
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if (pwr_off_in_progress)
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return EINVAL;
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use_count++;
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if (rtc.mapped_addr != 0) {
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/* already intialized */
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return OK;
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}
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/* Enable Clocks */
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r = omap_rtc_clkconf();
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if (r != OK) {
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log_warn(&log, "Failed to enable clocks for RTC.\n");
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return r;
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}
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/*
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* Map RTC_SS Registers
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*/
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/* Configure memory access */
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mr.mr_base = rtc.mr_base; /* start addr */
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mr.mr_limit = mr.mr_base + rtc.mr_size; /* end addr */
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/* ask for privileges to access the RTC_SS memory range */
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if (sys_privctl(SELF, SYS_PRIV_ADD_MEM, &mr) != OK) {
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log_warn(&log,
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"Unable to obtain RTC memory range privileges.");
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return EPERM;
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}
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/* map the memory into this process */
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rtc.mapped_addr = (vir_bytes) vm_map_phys(SELF,
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(void *) rtc.mr_base, rtc.mr_size);
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if (rtc.mapped_addr == (vir_bytes) MAP_FAILED) {
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log_warn(&log, "Unable to map RTC registers\n");
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return EPERM;
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}
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rtc_rev = reg_read(rtc.regs->RTC_SS_RTC_REVISION);
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major = (rtc_rev & 0x0700) >> 8;
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minor = (rtc_rev & 0x001f);
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log_debug(&log, "omap rtc rev %d.%d\n", major, minor);
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/* Disable register write protect */
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omap_rtc_unlock();
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/* Set NOIDLE */
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reg_write(rtc.regs->RTC_SS_RTC_SYSCONFIG, (1 << NOIDLE_BIT));
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/* Enable 32kHz clock */
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reg_set_bit(rtc.regs->RTC_SS_RTC_OSC_REG, EN_32KCLK_BIT);
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/* Setting the stop bit starts the RTC running */
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reg_set_bit(rtc.regs->RTC_SS_RTC_CTRL_REG, RTC_STOP_BIT);
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/* Re-enable Write Protection */
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omap_rtc_lock();
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log_debug(&log, "OMAP RTC Initialized\n");
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return OK;
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}
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/*
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* These are the ranges used by the real time clock and struct tm.
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*
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* Field OMAP RTC struct tm
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* ----- -------- ---------
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* seconds 0 to 59 (Mask 0x7f) 0 to 59 (60 for leap seconds)
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* minutes 0 to 59 (Mask 0x7f) 0 to 59
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* hours 0 to 23 (Mask 0x3f) 0 to 23
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* day 1 to 31 (Mask 0x3f) 1 to 31
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* month 1 to 12 (Mask 0x1f) 0 to 11
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* year last 2 digits of year X + 1900
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*/
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int
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omap_rtc_get_time(struct tm *t, int flags)
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{
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int r;
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if (pwr_off_in_progress)
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return EINVAL;
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memset(t, '\0', sizeof(struct tm));
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/* Read and Convert BCD to binary (default RTC mode). */
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t->tm_sec = bcd_to_dec(reg_read(rtc.regs->RTC_SS_SECONDS_REG) & 0x7f);
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t->tm_min = bcd_to_dec(reg_read(rtc.regs->RTC_SS_MINUTES_REG) & 0x7f);
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t->tm_hour = bcd_to_dec(reg_read(rtc.regs->RTC_SS_HOURS_REG) & 0x3f);
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t->tm_mday = bcd_to_dec(reg_read(rtc.regs->RTC_SS_DAYS_REG) & 0x3f);
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t->tm_mon =
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bcd_to_dec(reg_read(rtc.regs->RTC_SS_MONTHS_REG) & 0x1f) - 1;
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t->tm_year =
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bcd_to_dec(reg_read(rtc.regs->RTC_SS_YEARS_REG) & 0xff) + 100;
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if (t->tm_year == 100) {
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/* Cold start - no date/time set - default to 2013-01-01 */
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t->tm_sec = 0;
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t->tm_min = 0;
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t->tm_hour = 0;
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t->tm_mday = 1;
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t->tm_mon = 0;
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t->tm_year = 113;
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omap_rtc_set_time(t, RTCDEV_NOFLAGS);
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}
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return OK;
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}
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int
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omap_rtc_set_time(struct tm *t, int flags)
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{
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int r;
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if (pwr_off_in_progress)
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return EINVAL;
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/* Disable Write Protection */
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omap_rtc_unlock();
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/* Write the date/time to the RTC registers. */
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safe_reg_write(rtc.regs->RTC_SS_SECONDS_REG,
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(dec_to_bcd(t->tm_sec) & 0x7f));
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safe_reg_write(rtc.regs->RTC_SS_MINUTES_REG,
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(dec_to_bcd(t->tm_min) & 0x7f));
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safe_reg_write(rtc.regs->RTC_SS_HOURS_REG,
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(dec_to_bcd(t->tm_hour) & 0x3f));
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safe_reg_write(rtc.regs->RTC_SS_DAYS_REG,
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(dec_to_bcd(t->tm_mday) & 0x3f));
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safe_reg_write(rtc.regs->RTC_SS_MONTHS_REG,
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(dec_to_bcd(t->tm_mon + 1) & 0x1f));
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safe_reg_write(rtc.regs->RTC_SS_YEARS_REG,
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(dec_to_bcd(t->tm_year % 100) & 0xff));
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/* Re-enable Write Protection */
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omap_rtc_lock();
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return OK;
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}
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int
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omap_rtc_pwr_off(void)
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{
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int r;
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struct tm t;
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if (pwr_off_in_progress)
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return EINVAL;
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/* wait until 3 seconds can be added without overflowing tm_sec */
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do {
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omap_rtc_get_time(&t, RTCDEV_NOFLAGS);
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micro_delay(250000);
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} while (t.tm_sec >= 57);
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/* set the alarm for 3 seconds from now */
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t.tm_sec += 3;
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/* Disable register write protect */
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omap_rtc_unlock();
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/* enable power-off via ALARM2 by setting the PWR_ENABLE_EN bit. */
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safe_reg_set_bit(rtc.regs->RTC_SS_RTC_PMIC, PWR_ENABLE_EN_BIT);
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/* Write the date/time to the RTC registers. */
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safe_reg_write(rtc.regs->RTC_SS_ALARM2_SECONDS_REG,
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(dec_to_bcd(t.tm_sec) & 0x7f));
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safe_reg_write(rtc.regs->RTC_SS_ALARM2_MINUTES_REG,
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(dec_to_bcd(t.tm_min) & 0x7f));
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safe_reg_write(rtc.regs->RTC_SS_ALARM2_HOURS_REG,
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(dec_to_bcd(t.tm_hour) & 0x3f));
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safe_reg_write(rtc.regs->RTC_SS_ALARM2_DAYS_REG,
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(dec_to_bcd(t.tm_mday) & 0x3f));
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safe_reg_write(rtc.regs->RTC_SS_ALARM2_MONTHS_REG,
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(dec_to_bcd(t.tm_mon + 1) & 0x1f));
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safe_reg_write(rtc.regs->RTC_SS_ALARM2_YEARS_REG,
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(dec_to_bcd(t.tm_year % 100) & 0xff));
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/* enable interrupt to trigger POWER_EN to go low when alarm2 hits. */
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safe_reg_set_bit(rtc.regs->RTC_SS_RTC_INTERRUPTS_REG, IT_ALARM2_BIT);
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/* pause the realtime clock. the kernel will enable it when safe. */
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reg_clear_bit(rtc.regs->RTC_SS_RTC_CTRL_REG, RTC_STOP_BIT);
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/* Set this flag to block all other operations so that the clock isn't
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* accidentally re-startered and so write protect isn't re-enabled. */
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pwr_off_in_progress = 1;
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/* Make the kernel's job easier by not re-enabling write protection */
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return OK;
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}
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void
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omap_rtc_exit(void)
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{
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use_count--;
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if (use_count == 0) {
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vm_unmap_phys(SELF, (void *) rtc.mapped_addr, rtc.mr_size);
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rtc.mapped_addr = 0;
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}
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log_debug(&log, "Exiting\n");
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}
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