496 lines
13 KiB
C
496 lines
13 KiB
C
#include "AC97.h"
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/* AC97 Mixer and Mode control function prototypes */
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static int AC97_write(const DEV_STRUCT * pCC, u16_t wAddr, u16_t
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wData);
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static int AC97_write_unsynced(const DEV_STRUCT * pCC, u16_t wAddr,
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u16_t wData);
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static int AC97_read_unsynced(const DEV_STRUCT * pCC, u16_t wAddr,
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u16_t *data);
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static void set_nice_volume(void);
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static int AC97_get_volume(struct volume_level *level);
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static int AC97_set_volume(const struct volume_level *level);
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#define AC97_0DB_GAIN 0x0008
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#define AC97_MAX_ATTN 0x003f
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#define AC97_MUTE 0x8000U
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/* Control function defines */
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#define AC97_CTL_4SPKR 0x00U /* 4-spkr output mode enable */
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#define AC97_CTL_MICBOOST 0x01U /* Mic boost (+30 dB) enable */
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#define AC97_CTL_PWRDOWN 0x02U /* power-down mode */
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#define AC97_CTL_DOSMODE 0x03U /* A/D sync to DAC1 */
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/* Timeout waiting for: */
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#define AC97_ERR_WIP_TIMEOUT -1 /* write in progress complete */
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#define AC97_ERR_DATA_TIMEOUT -2 /* data ready */
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#define AC97_ERR_SRC_NOT_BUSY_TIMEOUT -3 /* SRC not busy */
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#define AC97_ERR_SRC_SYNC_TIMEOUT -4 /* state #1 */
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/* Timeouts in milliseconds */
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#define WIP_TIMEOUT 250UL
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#define DRDY_TIMEOUT 250UL
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/* The default SRC syncronization state number is 1. This state occurs
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just after de-assertion of SYNC. This is supposed to be the safest
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state for accessing the codec with an ES1371 Rev 1. Later versions
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of the chip allegedly don't require syncronization. Be very careful
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if you change this ! */
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#define SRC_UNSYNCED 0xffffffffUL
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static u32_t SrcSyncState = 0x00010000UL;
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static DEV_STRUCT *dev;
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#if 0
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static void set_src_sync_state (int state)
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{
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if (state < 0)
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SrcSyncState = SRC_UNSYNCED;
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else {
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SrcSyncState = (u32_t)state << 16;
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SrcSyncState &= 0x00070000Ul;
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}
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}
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#endif
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static int AC97_write (const DEV_STRUCT * pCC, u16_t wAddr, u16_t wData)
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{
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u32_t dtemp, i;
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u16_t wBaseAddr = pCC->base;
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/* wait for WIP bit (Write In Progress) to go away */
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/* remember, register CODEC_READ (0x14)
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is a pseudo read-write register */
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if (WaitBitd (wBaseAddr + CODEC_READ, 30, 0, WIP_TIMEOUT)){
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printf("AC97_ERR_WIP_TIMEOUT\n");
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return (AC97_ERR_WIP_TIMEOUT);
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}
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if (SRC_UNSYNCED != SrcSyncState)
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{
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/* enable SRC state data in SRC mux */
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if (WaitBitd (wBaseAddr + SAMPLE_RATE_CONV, SRC_BUSY_BIT, 0, 1000))
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return (AC97_ERR_SRC_NOT_BUSY_TIMEOUT);
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/* todo: why are we writing an undefined register? */
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dtemp = pci_inl(wBaseAddr + SAMPLE_RATE_CONV);
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pci_outl(wBaseAddr + SAMPLE_RATE_CONV, (dtemp & SRC_CTLMASK) |
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0x00010000UL);
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/* wait for a SAFE time to write addr/data and then do it */
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/*_disable(); */
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for( i = 0; i < 0x1000UL; ++i )
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if( (pci_inl(wBaseAddr + SAMPLE_RATE_CONV) & 0x00070000UL) ==
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SrcSyncState )
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break;
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if (i >= 0x1000UL) {
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/* _enable(); */
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return (AC97_ERR_SRC_SYNC_TIMEOUT);
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}
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}
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/* A test for 5880 - prime the PCI data bus */
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{
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u32_t dat = ((u32_t) wAddr << 16) | wData;
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char page = pci_inb(wBaseAddr + MEM_PAGE);
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pci_outl (wBaseAddr + MEM_PAGE, dat);
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/* write addr and data */
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pci_outl(wBaseAddr + CODEC_READ, dat);
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pci_outb(wBaseAddr + MEM_PAGE, page); /* restore page reg */
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}
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if (SRC_UNSYNCED != SrcSyncState)
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{
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/* _enable(); */
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/* restore SRC reg */
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if (WaitBitd (wBaseAddr + SAMPLE_RATE_CONV, SRC_BUSY_BIT, 0, 1000))
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return (AC97_ERR_SRC_NOT_BUSY_TIMEOUT);
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pci_outl(wBaseAddr + SAMPLE_RATE_CONV, dtemp & 0xfff8ffffUL);
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}
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return 0;
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}
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#if 0
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static int AC97_read (const DEV_STRUCT * pCC, u16_t wAddr, u16_t *data)
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{
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u32_t dtemp, i;
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u16_t base = pCC->base;
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/* wait for WIP to go away */
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if (WaitBitd (base + CODEC_READ, 30, 0, WIP_TIMEOUT))
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return (AC97_ERR_WIP_TIMEOUT);
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if (SRC_UNSYNCED != SrcSyncState)
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{
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/* enable SRC state data in SRC mux */
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if (WaitBitd (base + SAMPLE_RATE_CONV, SRC_BUSY_BIT, 0, 1000))
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return (AC97_ERR_SRC_NOT_BUSY_TIMEOUT);
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dtemp = pci_inl(base + SAMPLE_RATE_CONV);
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pci_outl(base + SAMPLE_RATE_CONV, (dtemp & SRC_CTLMASK) |
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0x00010000UL);
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/* wait for a SAFE time to write a read request and then do it */
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/* todo: how do we solve the lock() problem? */
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/* _disable(); */
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for( i = 0; i < 0x1000UL; ++i )
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if( (pci_inl(base + SAMPLE_RATE_CONV) & 0x00070000UL) ==
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SrcSyncState )
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break;
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if (i >= 0x1000UL) {
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/*_enable();*/
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return (AC97_ERR_SRC_SYNC_TIMEOUT);
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}
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}
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/* A test for 5880 - prime the PCI data bus */
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{
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/* set bit 23, this means read in stead of write. */
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u32_t dat = ((u32_t) wAddr << 16) | (1UL << 23);
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char page = pci_inb(base + MEM_PAGE);
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/* todo: why are we putting data in the mem page register??? */
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pci_outl(base + MEM_PAGE, dat);
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/* write addr w/data=0 and assert read request */
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pci_outl(base + CODEC_READ, dat);
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pci_outb(base + MEM_PAGE, page); /* restore page reg */
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}
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if (SRC_UNSYNCED != SrcSyncState)
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{
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/*_enable();*/
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/* restore SRC reg */
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if (WaitBitd (base + SAMPLE_RATE_CONV, SRC_BUSY_BIT, 0, 1000))
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return (AC97_ERR_SRC_NOT_BUSY_TIMEOUT);
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pci_outl(base + SAMPLE_RATE_CONV, dtemp & 0xfff8ffffUL);
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}
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/* now wait for the stinkin' data (DRDY = data ready) */
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if (WaitBitd (base + CODEC_READ, 31, 1, DRDY_TIMEOUT))
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return (AC97_ERR_DATA_TIMEOUT);
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dtemp = pci_inl(base + CODEC_READ);
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if (data)
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*data = (u16_t) dtemp;
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return 0;
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}
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#endif
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static int AC97_write_unsynced (const DEV_STRUCT * pCC, u16_t wAddr,
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u16_t wData)
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{
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/* wait for WIP to go away */
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if (WaitBitd (pCC->base + CODEC_READ, 30, 0, WIP_TIMEOUT))
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return (AC97_ERR_WIP_TIMEOUT);
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/* write addr and data */
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pci_outl(pCC->base + CODEC_READ, ((u32_t) wAddr << 16) | wData);
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return 0;
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}
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static int AC97_read_unsynced (const DEV_STRUCT * pCC, u16_t wAddr,
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u16_t *data)
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{
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u32_t dtemp;
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/* wait for WIP to go away */
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if (WaitBitd (pCC->base + CODEC_READ, 30, 0, WIP_TIMEOUT))
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return (AC97_ERR_WIP_TIMEOUT);
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/* write addr w/data=0 and assert read request */
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pci_outl(pCC->base + CODEC_READ, ((u32_t) wAddr << 16) | (1UL << 23));
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/* now wait for the stinkin' data (RDY) */
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if (WaitBitd (pCC->base + CODEC_READ, 31, 1, DRDY_TIMEOUT))
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return (AC97_ERR_DATA_TIMEOUT);
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dtemp = pci_inl(pCC->base + CODEC_READ);
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if (data)
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*data = (u16_t) dtemp;
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return 0;
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}
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int AC97_init( DEV_STRUCT * pCC ) {
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int retVal;
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/* All powerdown modes: off */
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dev = pCC;
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retVal = AC97_write (pCC, AC97_POWERDOWN_CONTROL_STAT, 0x0000U);
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if (OK != retVal)
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return (retVal);
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/* Mute Line Out & set to 0dB attenuation */
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retVal = AC97_write (pCC, AC97_MASTER_VOLUME, 0x0000U);
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if (OK != retVal)
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return (retVal);
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retVal = AC97_write (pCC, AC97_MONO_VOLUME, 0x8000U);
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if (OK != retVal)
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return (retVal);
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retVal = AC97_write (pCC, AC97_PHONE_VOLUME, 0x8008U);
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if (OK != retVal)
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return (retVal);
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retVal = AC97_write (pCC, AC97_MIC_VOLUME, 0x0008U);
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if (OK != retVal)
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return (retVal);
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retVal = AC97_write (pCC, AC97_LINE_IN_VOLUME, 0x0808U);
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if (OK != retVal)
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return (retVal);
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retVal = AC97_write (pCC, AC97_CD_VOLUME, 0x0808U);
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if (OK != retVal)
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return (retVal);
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retVal = AC97_write (pCC, AC97_AUX_IN_VOLUME, 0x0808U);
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if (OK != retVal)
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return (retVal);
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retVal = AC97_write (pCC, AC97_PCM_OUT_VOLUME, 0x0808U);
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if (OK != retVal)
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return (retVal);
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retVal = AC97_write (pCC, AC97_RECORD_GAIN_VOLUME, 0x0000U);
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if (OK != retVal)
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return (retVal);
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/* Connect Line In to ADC */
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retVal = AC97_write (pCC, AC97_RECORD_SELECT, 0x0404U);
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if (OK != retVal)
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return (retVal);
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retVal = AC97_write (pCC, AC97_GENERAL_PURPOSE, 0x0000U);
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if (OK != retVal)
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return (retVal);
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set_nice_volume();
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return OK;
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}
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static void set_nice_volume(void) {
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/* goofy code to set the DAC1 channel to an audibe volume
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to be able to test it without using the mixer */
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AC97_write_unsynced(dev, AC97_PCM_OUT_VOLUME, 0x0808);/* the higher,
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the softer */
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AC97_write_unsynced(dev, AC97_MASTER_VOLUME, 0x0101);
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AC97_write_unsynced(dev, 0x38, 0); /* not crucial */
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AC97_write_unsynced(dev, AC97_LINE_IN_VOLUME, 0x0303);
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AC97_write_unsynced(dev, AC97_MIC_VOLUME, 0x005f);
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/* mute record gain */
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AC97_write_unsynced(dev, AC97_RECORD_GAIN_VOLUME, 0xFFFF);
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/* mic record volume high */
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AC97_write_unsynced(dev, AC97_RECORD_GAIN_MIC_VOL, 0x0000);
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/* Also, to be able test recording without mixer:
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select ONE channel as input below. */
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/* select LINE IN */
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/*AC97_write_unsynced(dev, AC97_RECORD_SELECT, 0x0404);*/
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/* select MIC */
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AC97_write_unsynced(dev, AC97_RECORD_SELECT, 0x0000);
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/* unmute record gain */
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AC97_write_unsynced(dev, AC97_RECORD_GAIN_VOLUME, 0x0000);
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}
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static int get_volume(u8_t *left, u8_t *right, int cmd) {
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u16_t value;
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AC97_read_unsynced(dev, (u16_t)cmd, &value);
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*left = value>>8;
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*right = value&0xff;
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return OK;
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}
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static int set_volume(int left, int right, int cmd) {
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u16_t waarde;
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waarde = (u16_t)((left<<8)|right);
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AC97_write_unsynced(dev, (u16_t)cmd, waarde);
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return OK;
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}
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void convert(int left_in, int right_in, int max_in, int *left_out,
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int *right_out, int max_out, int swaplr) {
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int tmp;
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if(left_in < 0) left_in = 0;
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else if(left_in > max_in) left_in = max_in;
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if(right_in < 0) right_in = 0;
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else if(right_in > max_in) right_in = max_in;
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if (swaplr) {
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tmp = left_in;
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left_in = right_in;
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right_in = tmp;
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}
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*left_out = (-left_in) + max_out;
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*right_out = (-right_in) + max_out;
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}
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int AC97_get_set_volume(struct volume_level *level, int flag) {
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if (flag) {
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return AC97_set_volume(level);
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}
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else {
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return AC97_get_volume(level);
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}
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}
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static int AC97_get_volume(struct volume_level *level) {
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int cmd;
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u8_t left;
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u8_t right;
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switch(level->device) {
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case Master:
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cmd = AC97_MASTER_VOLUME;
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get_volume(&left, &right, cmd);
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convert(left, right, 0x1f,
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&(level->left), &(level->right), 0x1f, 0);
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break;
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case Dac:
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return EINVAL;
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break;
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case Fm:
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cmd = AC97_PCM_OUT_VOLUME;
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get_volume(&left, &right, cmd);
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convert(left, right, 0x1f,
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&(level->left), &(level->right), 0x1f, 0);
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break;
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case Cd:
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cmd = AC97_CD_VOLUME;
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get_volume(&left, &right, cmd);
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convert(left, right, 0x1f,
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&(level->left), &(level->right), 0x1f, 0);
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break;
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case Line:
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cmd = AC97_LINE_IN_VOLUME;
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get_volume(&left, &right, cmd);
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convert(left, right, 0x1f,
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&(level->left), &(level->right), 0x1f, 0);
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break;
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case Mic:
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cmd = AC97_MIC_VOLUME;
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get_volume(&left, &right, cmd);
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convert(left, right, 0x1f,
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&(level->left), &(level->right), 0x1f, 1);
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break;
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case Speaker:
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return EINVAL;
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case Treble:
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cmd = AC97_MASTER_TONE;
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get_volume(&left, &right, cmd);
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convert(left, right, 0xf,
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&(level->left), &(level->right), 0xf, 1);
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break;
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case Bass:
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cmd = AC97_MASTER_TONE;
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get_volume(&left, &right, cmd);
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convert(left, right, 0xf,
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&(level->left), &(level->right), 0xf, 1);
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break;
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default:
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return EINVAL;
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}
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return OK;
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}
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static int AC97_set_volume(const struct volume_level *level) {
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int cmd;
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int left;
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int right;
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switch(level->device) {
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case Master:
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cmd = AC97_MASTER_VOLUME;
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convert(level->left, level->right, 0x1f, &left, &right, 0x1f, 0);
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break;
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case Dac:
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return EINVAL;
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case Fm:
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cmd = AC97_PCM_OUT_VOLUME;
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convert(level->left, level->right, 0x1f, &left, &right, 0x1f, 0);
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break;
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case Cd:
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cmd = AC97_CD_VOLUME;
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convert(level->left, level->right, 0x1f, &left, &right, 0x1f, 0);
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break;
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case Line:
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cmd = AC97_LINE_IN_VOLUME;
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convert(level->left, level->right, 0x1f, &left, &right, 0x1f, 0);
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break;
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case Mic:
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cmd = AC97_MIC_VOLUME;
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convert(level->left, level->right, 0x1f, &left, &right, 0x1f, 1);
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break;
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case Speaker:
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return EINVAL;
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case Treble:
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return EINVAL;
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case Bass:
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return EINVAL;
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default:
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return EINVAL;
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}
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set_volume(left, right, cmd);
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return OK;
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}
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