570 lines
16 KiB
C
Executable file
570 lines
16 KiB
C
Executable file
/*
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* Implementation of low level MUSB core logic (variant independent)
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*/
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#include <string.h> /* memcpy */
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#include <time.h> /* nanosleep */
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#include <usb/hcd_common.h>
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#include <usb/hcd_interface.h>
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#include <usb/usb_common.h>
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#include "musb_core.h"
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#include "musb_regs.h"
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/*===========================================================================*
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* Local defines *
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*===========================================================================*/
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#define HCD_COPYBUF_BYTES 64 /* Stack allocated, must be multiple of 4 */
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#define HCD_COPYBUF_WORDS (HCD_COPYBUF_BYTES/4)
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/*===========================================================================*
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* Local prototypes *
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*===========================================================================*/
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static void musb_set_state(musb_core_config *);
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static int musb_check_rxpktrdy(void *);
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static void musb_in_stage_cleanup(void *);
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static void musb_clear_rxpktrdy(void *);
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static void musb_clear_statuspkt(void *);
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static int musb_get_count(void *);
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static void musb_read_fifo(void *, hcd_reg1 *, int, int);
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/*===========================================================================*
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* *
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* MUSB core implementation *
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* *
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*===========================================================================*/
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/*===========================================================================*
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* musb_set_state *
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*===========================================================================*/
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static void
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musb_set_state(musb_core_config * cfg)
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{
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void * r;
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hcd_reg1 idx;
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DEBUG_DUMP;
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r = cfg->regs;
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/* Set EP and address to be used in next MUSB command */
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/* Set EP by selecting INDEX */
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idx = HCD_RD1(r, MUSB_REG_INDEX);
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HCD_CLR(idx, 0x0F);
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HCD_SET(idx, cfg->ep & 0x0F);
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HCD_WR1(r, MUSB_REG_INDEX, idx);
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/* Use device with address 'cfg->addr' */
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HCD_WR2(r, MUSB_REG_RXFUNCADDR, cfg->addr);
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HCD_WR2(r, MUSB_REG_TXFUNCADDR, cfg->addr);
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}
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/*===========================================================================*
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* musb_check_rxpktrdy *
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*===========================================================================*/
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static int
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musb_check_rxpktrdy(void * cfg)
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{
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void * r;
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hcd_reg2 host_csr0;
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DEBUG_DUMP;
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r = ((musb_core_config *)cfg)->regs;
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/* Set EP and device address to be used in this command */
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musb_set_state((musb_core_config *)cfg);
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/* Get control status register for EP 0 */
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host_csr0 = HCD_RD2(r, MUSB_REG_HOST_CSR0);
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/* Check for RXPKTRDY */
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if (host_csr0 & MUSB_VAL_HOST_CSR0_RXPKTRDY)
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return EXIT_SUCCESS;
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return EXIT_FAILURE;
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}
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/*===========================================================================*
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* musb_in_stage_cleanup *
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*===========================================================================*/
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static void
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musb_in_stage_cleanup(void * cfg)
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{
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DEBUG_DUMP;
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musb_clear_rxpktrdy(cfg);
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musb_clear_statuspkt(cfg);
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}
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/*===========================================================================*
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* musb_clear_rxpktrdy *
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*===========================================================================*/
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static void
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musb_clear_rxpktrdy(void * cfg)
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{
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void * r;
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hcd_reg2 host_csr0;
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DEBUG_DUMP;
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r = ((musb_core_config *)cfg)->regs;
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/* Set EP and device address to be used in this command */
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musb_set_state((musb_core_config *)cfg);
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/* Get control status register for EP 0 */
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host_csr0 = HCD_RD2(r, MUSB_REG_HOST_CSR0);
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/* Clear RXPKTRDY to signal receive completion */
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HCD_CLR(host_csr0, MUSB_VAL_HOST_CSR0_RXPKTRDY);
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HCD_WR2(r, MUSB_REG_HOST_CSR0, host_csr0);
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}
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/*===========================================================================*
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* musb_clear_statuspkt *
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*===========================================================================*/
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static void
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musb_clear_statuspkt(void * cfg)
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{
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void * r;
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hcd_reg2 host_csr0;
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DEBUG_DUMP;
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r = ((musb_core_config *)cfg)->regs;
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/* Set EP and device address to be used in this command */
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musb_set_state((musb_core_config *)cfg);
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/* Get control status register for EP 0 */
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host_csr0 = HCD_RD2(r, MUSB_REG_HOST_CSR0);
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/* Clear STATUSPKT to signal status packet completion */
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HCD_CLR(host_csr0, MUSB_VAL_HOST_CSR0_STATUSPKT);
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HCD_WR2(r, MUSB_REG_HOST_CSR0, host_csr0);
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}
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/*===========================================================================*
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* musb_get_count *
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*===========================================================================*/
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static int
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musb_get_count(void * cfg)
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{
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void * r;
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DEBUG_DUMP;
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r = ((musb_core_config *)cfg)->regs;
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/* Set EP and device address to be used in this command */
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musb_set_state((musb_core_config *)cfg);
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/* Reserved part returns zero so no need to generalize
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* this return for MUSB_REG_RXCOUNT */
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return (int)(HCD_RD2(r, MUSB_REG_COUNT0));
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}
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/*===========================================================================*
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* musb_read_fifo *
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*===========================================================================*/
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static void
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musb_read_fifo(void * cfg, hcd_reg1 * output, int size, int fifo_num)
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{
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void * r;
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hcd_reg4 * word;
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hcd_reg4 copy_buf[HCD_COPYBUF_WORDS];
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hcd_addr fifo_addr;
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int limit;
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int idx;
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DEBUG_DUMP;
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USB_ASSERT((fifo_num >= 0) && (fifo_num <= 4), "Wrong FIFO number");
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r = ((musb_core_config *)cfg)->regs;
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fifo_addr = MUSB_REG_FIFO0 + (fifo_num * MUSB_REG_FIFO_LEN);
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/* Set EP and device address to be used in this command */
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musb_set_state((musb_core_config *)cfg);
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/* Read full words from MUSB FIFO */
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while (size > 0) {
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/* Largest amount of bytes that can be copied at a time */
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limit = (size < HCD_COPYBUF_BYTES) ? size : HCD_COPYBUF_BYTES;
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/* Start copying into that */
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word = copy_buf;
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/* Read words from FIFO into copy_buf */
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for (idx = 0; idx < limit; idx += sizeof(*word))
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*word++ = HCD_RD4(r, fifo_addr);
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/* Copy and shift */
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memcpy(output, copy_buf, limit);
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output += limit;
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size -= limit;
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}
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}
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/*===========================================================================*
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* musb_core_start *
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*===========================================================================*/
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void
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musb_core_start(void * cfg)
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{
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void * r;
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hcd_reg1 devctl;
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DEBUG_DUMP;
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r = ((musb_core_config *)cfg)->regs;
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/* Enable all interrupts valid for host */
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HCD_WR1(r, MUSB_REG_INTRUSBE,
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MUSB_VAL_INTRUSBE_SUSPEND |
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MUSB_VAL_INTRUSBE_RESUME |
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MUSB_VAL_INTRUSBE_RESET_BABBLE |
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/* MUSB_VAL_INTRUSBE_SOF | */
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MUSB_VAL_INTRUSBE_CONN |
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MUSB_VAL_INTRUSBE_DISCON |
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MUSB_VAL_INTRUSBE_SESSREQ |
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MUSB_VAL_INTRUSBE_VBUSERR);
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/* Start session */
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devctl = HCD_RD1(r, MUSB_REG_DEVCTL);
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HCD_SET(devctl, MUSB_VAL_DEVCTL_SESSION);
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HCD_WR1(r, MUSB_REG_DEVCTL, devctl);
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}
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/*===========================================================================*
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* musb_core_stop *
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*===========================================================================*/
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void
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musb_core_stop(void * cfg)
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{
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void * r;
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hcd_reg1 devctl;
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DEBUG_DUMP;
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r = ((musb_core_config *)cfg)->regs;
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/* TODO: add hardware interrupt disable */
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/* Stop session */
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devctl = HCD_RD1(r, MUSB_REG_DEVCTL);
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HCD_CLR(devctl, MUSB_VAL_DEVCTL_SESSION);
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HCD_WR1(r, MUSB_REG_DEVCTL, devctl);
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}
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/*===========================================================================*
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* musb_ep0_config *
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*===========================================================================*/
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void
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musb_ep0_config(void * cfg)
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{
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void * r;
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hcd_reg1 host_type0;
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hcd_reg2 intrtxe;
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DEBUG_DUMP;
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r = ((musb_core_config *)cfg)->regs;
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/* Set parameters temporarily */
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musb_setup_device((musb_core_config *)cfg,
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HCD_DEFAULT_EP,
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HCD_DEFAULT_ADDR);
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/* Set EP and device address to be used in this command */
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musb_set_state((musb_core_config *)cfg);
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/* Set high speed for EP0 */
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host_type0 = HCD_RD1(r, MUSB_REG_HOST_TYPE0);
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HCD_CLR(host_type0, MUSB_VAL_HOST_TYPE0_MASK);
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HCD_SET(host_type0, MUSB_VAL_HOST_TYPE0_HIGH_SPEED);
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HCD_WR1(r, MUSB_REG_HOST_TYPE0, host_type0);
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/* Enable EP interrupt */
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intrtxe = HCD_RD2(r, MUSB_REG_INTRTXE);
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HCD_SET(intrtxe, MUSB_VAL_INTRTXE_EP0);
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HCD_WR2(r, MUSB_REG_INTRTXE, intrtxe);
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}
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/*===========================================================================*
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* *
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* HCD interface implementation *
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* *
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*===========================================================================*/
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/*===========================================================================*
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* musb_setup_device *
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*===========================================================================*/
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void
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musb_setup_device(void * cfg, hcd_reg1 ep, hcd_reg1 addr)
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{
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DEBUG_DUMP;
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/* Assign */
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((musb_core_config *)cfg)->ep = ep;
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((musb_core_config *)cfg)->addr = addr;
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}
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/*===========================================================================*
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* musb_reset_device *
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*===========================================================================*/
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void
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musb_reset_device(void * cfg)
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{
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void * r;
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hcd_reg1 power;
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DEBUG_DUMP;
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r = ((musb_core_config *)cfg)->regs;
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/* Write reset bit and high speed negotiation wait for at least
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* 20ms for reset, clear reset bit and wait for device */
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power = HCD_RD1(r, MUSB_REG_POWER);
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HCD_SET(power, MUSB_VAL_POWER_RESET | MUSB_VAL_POWER_HSEN);
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HCD_WR1(r, MUSB_REG_POWER, power);
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{
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/* Sleep 25ms */
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struct timespec nanotm = {0, HCD_NANOSLEEP_MSEC(25)};
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nanosleep(&nanotm, NULL);
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}
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power = HCD_RD1(r, MUSB_REG_POWER);
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HCD_CLR(power, MUSB_VAL_POWER_RESET);
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HCD_WR1(r, MUSB_REG_POWER, power);
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{
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/* Sleep 25ms */
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struct timespec nanotm = {0, HCD_NANOSLEEP_MSEC(25)};
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nanosleep(&nanotm, NULL);
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}
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}
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/*===========================================================================*
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* musb_setup_stage *
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*===========================================================================*/
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void
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musb_setup_stage(void * cfg, hcd_ctrlrequest * setup)
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{
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void * r;
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char * setup_byte;
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hcd_reg2 host_csr0;
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DEBUG_DUMP;
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r = ((musb_core_config *)cfg)->regs;
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setup_byte = (char*)setup;
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/* Set EP and device address to be used in this command */
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musb_set_state((musb_core_config *)cfg);
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/* TODO: check for ongoing transmission */
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/* Put USB setup data into corresponding FIFO */
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HCD_WR4(r, MUSB_REG_FIFO0, HCD_8TO32(&setup_byte[0]));
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HCD_WR4(r, MUSB_REG_FIFO0, HCD_8TO32(&setup_byte[sizeof(hcd_reg4)]));
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/* Get control status register for EP 0 */
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host_csr0 = HCD_RD2(r, MUSB_REG_HOST_CSR0);
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/* Send actual packet from FIFO */
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HCD_SET(host_csr0, MUSB_VAL_HOST_CSR0_TXPKTRDY |
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MUSB_VAL_HOST_CSR0_SETUPPKT);
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HCD_WR2(r, MUSB_REG_HOST_CSR0, host_csr0);
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}
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/*===========================================================================*
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* musb_in_data_stage *
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*===========================================================================*/
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void
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musb_in_data_stage(void * cfg)
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{
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void * r;
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hcd_reg2 host_csr0;
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DEBUG_DUMP;
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r = ((musb_core_config *)cfg)->regs;
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/* Set EP and device address to be used in this command */
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musb_set_state((musb_core_config *)cfg);
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/* Get control status register for EP 0 */
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host_csr0 = HCD_RD2(r, MUSB_REG_HOST_CSR0);
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/* Request IN DATA stage */
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HCD_SET(host_csr0, MUSB_VAL_HOST_CSR0_REQPKT);
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HCD_WR2(r, MUSB_REG_HOST_CSR0, host_csr0);
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}
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/*===========================================================================*
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* musb_out_data_stage *
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*===========================================================================*/
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void
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musb_out_data_stage(void * cfg)
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{
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DEBUG_DUMP;
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/* Set EP and device address to be used in this command */
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musb_set_state((musb_core_config *)cfg);
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/* TODO: not needed for enumeration but will be needed later */
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((void)cfg);
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USB_MSG("NOT IMPLEMENTED");
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}
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/*===========================================================================*
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* musb_in_status_stage *
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*===========================================================================*/
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void
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musb_in_status_stage(void * cfg)
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{
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void * r;
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hcd_reg2 host_csr0;
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DEBUG_DUMP;
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r = ((musb_core_config *)cfg)->regs;
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/* Set EP and device address to be used in this command */
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musb_set_state((musb_core_config *)cfg);
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/* Get control status register for EP 0 */
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host_csr0 = HCD_RD2(r, MUSB_REG_HOST_CSR0);
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/* Request IN STATUS stage */
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HCD_SET(host_csr0, MUSB_VAL_HOST_CSR0_REQPKT |
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MUSB_VAL_HOST_CSR0_STATUSPKT);
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HCD_WR2(r, MUSB_REG_HOST_CSR0, host_csr0);
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}
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/*===========================================================================*
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* musb_out_status_stage *
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*===========================================================================*/
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void
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musb_out_status_stage(void * cfg)
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{
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void * r;
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hcd_reg2 host_csr0;
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DEBUG_DUMP;
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r = ((musb_core_config *)cfg)->regs;
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/* Set EP and device address to be used in this command */
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musb_set_state((musb_core_config *)cfg);
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/* Get control status register for EP 0 */
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host_csr0 = HCD_RD2(r, MUSB_REG_HOST_CSR0);
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/* Request OUT STATUS stage */
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HCD_SET(host_csr0, MUSB_VAL_HOST_CSR0_TXPKTRDY |
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MUSB_VAL_HOST_CSR0_STATUSPKT);
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HCD_WR2(r, MUSB_REG_HOST_CSR0, host_csr0);
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}
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/*===========================================================================*
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* musb_read_data *
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*===========================================================================*/
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int
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musb_read_data(void * cfg, hcd_reg1 * buffer, int buffer_num)
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{
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int count0;
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DEBUG_DUMP;
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/* Check if anything received at all */
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if (EXIT_SUCCESS != musb_check_rxpktrdy(cfg)) {
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USB_MSG("RXPKTRDY not set when receiving");
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return HCD_READ_ERR;
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}
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/* Number of bytes received at EP0 */
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count0 = musb_get_count(cfg);
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/* Read from given FIFO */
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if ((NULL != buffer) && (count0 > 0))
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musb_read_fifo(cfg, buffer, count0, buffer_num);
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/* Cleanup after reading */
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musb_in_stage_cleanup(cfg);
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return count0;
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}
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/*===========================================================================*
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* musb_check_error *
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*===========================================================================*/
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int
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musb_check_error(void * cfg)
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{
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void * r;
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hcd_reg2 host_csr0;
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DEBUG_DUMP;
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r = ((musb_core_config *)cfg)->regs;
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/* Set EP and device address to be used in this command */
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musb_set_state((musb_core_config *)cfg);
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/* Get control status register for EP 0 */
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host_csr0 = HCD_RD2(r, MUSB_REG_HOST_CSR0);
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/* Check for common errors */
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if (host_csr0 & MUSB_VAL_HOST_CSR0_ERROR) {
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USB_MSG("HOST_CSR0 ERROR: %04X", host_csr0);
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HCD_CLR(host_csr0, MUSB_VAL_HOST_CSR0_ERROR);
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|
HCD_WR2(r, MUSB_REG_HOST_CSR0, host_csr0);
|
|
return EXIT_FAILURE;
|
|
}
|
|
|
|
if (host_csr0 & MUSB_VAL_HOST_CSR0_RXSTALL) {
|
|
USB_MSG("HOST_CSR0 STALL: %04X", host_csr0);
|
|
HCD_CLR(host_csr0, MUSB_VAL_HOST_CSR0_RXSTALL);
|
|
HCD_WR2(r, MUSB_REG_HOST_CSR0, host_csr0);
|
|
return EXIT_FAILURE;
|
|
}
|
|
|
|
if (host_csr0 & MUSB_VAL_HOST_CSR0_NAK_TIMEOUT) {
|
|
USB_MSG("HOST_CSR0 NAK_TIMEOUT: %04X", host_csr0);
|
|
HCD_CLR(host_csr0, MUSB_VAL_HOST_CSR0_NAK_TIMEOUT);
|
|
HCD_WR2(r, MUSB_REG_HOST_CSR0, host_csr0);
|
|
return EXIT_FAILURE;
|
|
}
|
|
|
|
return EXIT_SUCCESS;
|
|
}
|