934 lines
30 KiB
C
934 lines
30 KiB
C
/* $NetBSD: pmap.h,v 1.112 2012/09/22 00:33:38 matt Exp $ */
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/*
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* Copyright (c) 2002, 2003 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Jason R. Thorpe & Steve C. Woodford for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Copyright (c) 1994,1995 Mark Brinicombe.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Mark Brinicombe
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _ARM32_PMAP_H_
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#define _ARM32_PMAP_H_
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#ifdef _KERNEL
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#include <arm/cpuconf.h>
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#include <arm/arm32/pte.h>
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#ifndef _LOCORE
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#if defined(_KERNEL_OPT)
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#include "opt_arm32_pmap.h"
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#endif
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#include <arm/cpufunc.h>
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#include <uvm/uvm_object.h>
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#endif
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/*
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* a pmap describes a processes' 4GB virtual address space. this
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* virtual address space can be broken up into 4096 1MB regions which
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* are described by L1 PTEs in the L1 table.
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*
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* There is a line drawn at KERNEL_BASE. Everything below that line
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* changes when the VM context is switched. Everything above that line
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* is the same no matter which VM context is running. This is achieved
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* by making the L1 PTEs for those slots above KERNEL_BASE reference
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* kernel L2 tables.
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*
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* The basic layout of the virtual address space thus looks like this:
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*
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* 0xffffffff
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* .
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* .
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* .
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* KERNEL_BASE
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* --------------------
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* .
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* .
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* .
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* 0x00000000
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*/
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/*
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* The number of L2 descriptor tables which can be tracked by an l2_dtable.
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* A bucket size of 16 provides for 16MB of contiguous virtual address
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* space per l2_dtable. Most processes will, therefore, require only two or
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* three of these to map their whole working set.
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*/
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#define L2_BUCKET_LOG2 4
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#define L2_BUCKET_SIZE (1 << L2_BUCKET_LOG2)
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/*
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* Given the above "L2-descriptors-per-l2_dtable" constant, the number
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* of l2_dtable structures required to track all possible page descriptors
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* mappable by an L1 translation table is given by the following constants:
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*/
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#define L2_LOG2 ((32 - L1_S_SHIFT) - L2_BUCKET_LOG2)
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#define L2_SIZE (1 << L2_LOG2)
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/*
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* tell MI code that the cache is virtually-indexed.
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* ARMv6 is physically-tagged but all others are virtually-tagged.
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*/
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#if (ARM_MMU_V6 + ARM_MMU_V7) > 0
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#define PMAP_CACHE_VIPT
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#else
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#define PMAP_CACHE_VIVT
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#endif
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#ifndef _LOCORE
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struct l1_ttable;
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struct l2_dtable;
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/*
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* Track cache/tlb occupancy using the following structure
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*/
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union pmap_cache_state {
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struct {
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union {
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u_int8_t csu_cache_b[2];
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u_int16_t csu_cache;
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} cs_cache_u;
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union {
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u_int8_t csu_tlb_b[2];
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u_int16_t csu_tlb;
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} cs_tlb_u;
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} cs_s;
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u_int32_t cs_all;
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};
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#define cs_cache_id cs_s.cs_cache_u.csu_cache_b[0]
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#define cs_cache_d cs_s.cs_cache_u.csu_cache_b[1]
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#define cs_cache cs_s.cs_cache_u.csu_cache
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#define cs_tlb_id cs_s.cs_tlb_u.csu_tlb_b[0]
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#define cs_tlb_d cs_s.cs_tlb_u.csu_tlb_b[1]
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#define cs_tlb cs_s.cs_tlb_u.csu_tlb
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/*
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* Assigned to cs_all to force cacheops to work for a particular pmap
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*/
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#define PMAP_CACHE_STATE_ALL 0xffffffffu
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/*
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* This structure is used by machine-dependent code to describe
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* static mappings of devices, created at bootstrap time.
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*/
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struct pmap_devmap {
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vaddr_t pd_va; /* virtual address */
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paddr_t pd_pa; /* physical address */
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psize_t pd_size; /* size of region */
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vm_prot_t pd_prot; /* protection code */
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int pd_cache; /* cache attributes */
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};
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/*
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* The pmap structure itself
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*/
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struct pmap {
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u_int8_t pm_domain;
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bool pm_remove_all;
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bool pm_activated;
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struct l1_ttable *pm_l1;
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pd_entry_t *pm_pl1vec;
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pd_entry_t pm_l1vec;
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union pmap_cache_state pm_cstate;
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struct uvm_object pm_obj;
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kmutex_t pm_obj_lock;
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#define pm_lock pm_obj.vmobjlock
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struct l2_dtable *pm_l2[L2_SIZE];
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struct pmap_statistics pm_stats;
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LIST_ENTRY(pmap) pm_list;
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};
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/*
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* Physical / virtual address structure. In a number of places (particularly
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* during bootstrapping) we need to keep track of the physical and virtual
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* addresses of various pages
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*/
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typedef struct pv_addr {
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SLIST_ENTRY(pv_addr) pv_list;
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paddr_t pv_pa;
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vaddr_t pv_va;
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vsize_t pv_size;
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uint8_t pv_cache;
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uint8_t pv_prot;
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} pv_addr_t;
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typedef SLIST_HEAD(, pv_addr) pv_addrqh_t;
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extern pv_addrqh_t pmap_freeq;
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extern pv_addr_t kernelstack;
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extern pv_addr_t abtstack;
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extern pv_addr_t fiqstack;
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extern pv_addr_t irqstack;
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extern pv_addr_t undstack;
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extern pv_addr_t idlestack;
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extern pv_addr_t systempage;
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extern pv_addr_t kernel_l1pt;
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/*
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* Determine various modes for PTEs (user vs. kernel, cacheable
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* vs. non-cacheable).
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*/
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#define PTE_KERNEL 0
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#define PTE_USER 1
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#define PTE_NOCACHE 0
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#define PTE_CACHE 1
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#define PTE_PAGETABLE 2
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/*
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* Flags that indicate attributes of pages or mappings of pages.
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*
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* The PVF_MOD and PVF_REF flags are stored in the mdpage for each
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* page. PVF_WIRED, PVF_WRITE, and PVF_NC are kept in individual
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* pv_entry's for each page. They live in the same "namespace" so
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* that we can clear multiple attributes at a time.
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*
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* Note the "non-cacheable" flag generally means the page has
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* multiple mappings in a given address space.
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*/
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#define PVF_MOD 0x01 /* page is modified */
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#define PVF_REF 0x02 /* page is referenced */
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#define PVF_WIRED 0x04 /* mapping is wired */
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#define PVF_WRITE 0x08 /* mapping is writable */
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#define PVF_EXEC 0x10 /* mapping is executable */
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#ifdef PMAP_CACHE_VIVT
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#define PVF_UNC 0x20 /* mapping is 'user' non-cacheable */
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#define PVF_KNC 0x40 /* mapping is 'kernel' non-cacheable */
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#define PVF_NC (PVF_UNC|PVF_KNC)
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#endif
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#ifdef PMAP_CACHE_VIPT
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#define PVF_NC 0x20 /* mapping is 'kernel' non-cacheable */
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#define PVF_MULTCLR 0x40 /* mapping is multi-colored */
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#endif
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#define PVF_COLORED 0x80 /* page has or had a color */
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#define PVF_KENTRY 0x0100 /* page entered via pmap_kenter_pa */
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#define PVF_KMPAGE 0x0200 /* page is used for kmem */
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#define PVF_DIRTY 0x0400 /* page may have dirty cache lines */
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#define PVF_KMOD 0x0800 /* unmanaged page is modified */
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#define PVF_KWRITE (PVF_KENTRY|PVF_WRITE)
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#define PVF_DMOD (PVF_MOD|PVF_KMOD|PVF_KMPAGE)
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/*
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* Commonly referenced structures
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*/
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extern int pmap_debug_level; /* Only exists if PMAP_DEBUG */
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/*
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* Macros that we need to export
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*/
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#define pmap_resident_count(pmap) ((pmap)->pm_stats.resident_count)
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#define pmap_wired_count(pmap) ((pmap)->pm_stats.wired_count)
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#define pmap_is_modified(pg) \
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(((pg)->mdpage.pvh_attrs & PVF_MOD) != 0)
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#define pmap_is_referenced(pg) \
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(((pg)->mdpage.pvh_attrs & PVF_REF) != 0)
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#define pmap_is_page_colored_p(md) \
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(((md)->pvh_attrs & PVF_COLORED) != 0)
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#define pmap_copy(dp, sp, da, l, sa) /* nothing */
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#define pmap_phys_address(ppn) (arm_ptob((ppn)))
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u_int arm32_mmap_flags(paddr_t);
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#define ARM32_MMAP_WRITECOMBINE 0x40000000
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#define ARM32_MMAP_CACHEABLE 0x20000000
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#define pmap_mmap_flags(ppn) arm32_mmap_flags(ppn)
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/*
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* Functions that we need to export
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*/
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void pmap_procwr(struct proc *, vaddr_t, int);
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void pmap_remove_all(pmap_t);
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bool pmap_extract(pmap_t, vaddr_t, paddr_t *);
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#define PMAP_NEED_PROCWR
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#define PMAP_GROWKERNEL /* turn on pmap_growkernel interface */
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#define PMAP_ENABLE_PMAP_KMPAGE /* enable the PMAP_KMPAGE flag */
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#if (ARM_MMU_V6 + ARM_MMU_V7) > 0
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#define PMAP_PREFER(hint, vap, sz, td) pmap_prefer((hint), (vap), (td))
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void pmap_prefer(vaddr_t, vaddr_t *, int);
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#endif
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void pmap_icache_sync_range(pmap_t, vaddr_t, vaddr_t);
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/* Functions we use internally. */
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#ifdef PMAP_STEAL_MEMORY
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void pmap_boot_pagealloc(psize_t, psize_t, psize_t, pv_addr_t *);
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void pmap_boot_pageadd(pv_addr_t *);
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vaddr_t pmap_steal_memory(vsize_t, vaddr_t *, vaddr_t *);
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#endif
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void pmap_bootstrap(vaddr_t, vaddr_t);
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void pmap_do_remove(pmap_t, vaddr_t, vaddr_t, int);
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int pmap_fault_fixup(pmap_t, vaddr_t, vm_prot_t, int);
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bool pmap_get_pde_pte(pmap_t, vaddr_t, pd_entry_t **, pt_entry_t **);
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bool pmap_get_pde(pmap_t, vaddr_t, pd_entry_t **);
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void pmap_set_pcb_pagedir(pmap_t, struct pcb *);
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void pmap_debug(int);
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void pmap_postinit(void);
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void vector_page_setprot(int);
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const struct pmap_devmap *pmap_devmap_find_pa(paddr_t, psize_t);
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const struct pmap_devmap *pmap_devmap_find_va(vaddr_t, vsize_t);
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/* Bootstrapping routines. */
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void pmap_map_section(vaddr_t, vaddr_t, paddr_t, int, int);
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void pmap_map_entry(vaddr_t, vaddr_t, paddr_t, int, int);
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vsize_t pmap_map_chunk(vaddr_t, vaddr_t, paddr_t, vsize_t, int, int);
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void pmap_link_l2pt(vaddr_t, vaddr_t, pv_addr_t *);
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void pmap_devmap_bootstrap(vaddr_t, const struct pmap_devmap *);
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void pmap_devmap_register(const struct pmap_devmap *);
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/*
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* Special page zero routine for use by the idle loop (no cache cleans).
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*/
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bool pmap_pageidlezero(paddr_t);
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#define PMAP_PAGEIDLEZERO(pa) pmap_pageidlezero((pa))
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/*
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* used by dumpsys to record the PA of the L1 table
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*/
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uint32_t pmap_kernel_L1_addr(void);
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/*
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* The current top of kernel VM
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*/
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extern vaddr_t pmap_curmaxkvaddr;
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/*
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* Useful macros and constants
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*/
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/* Virtual address to page table entry */
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static inline pt_entry_t *
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vtopte(vaddr_t va)
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{
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pd_entry_t *pdep;
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pt_entry_t *ptep;
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if (pmap_get_pde_pte(pmap_kernel(), va, &pdep, &ptep) == false)
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return (NULL);
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return (ptep);
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}
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/*
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* Virtual address to physical address
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*/
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static inline paddr_t
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vtophys(vaddr_t va)
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{
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paddr_t pa;
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if (pmap_extract(pmap_kernel(), va, &pa) == false)
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return (0); /* XXXSCW: Panic? */
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return (pa);
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}
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/*
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* The new pmap ensures that page-tables are always mapping Write-Thru.
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* Thus, on some platforms we can run fast and loose and avoid syncing PTEs
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* on every change.
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*
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* Unfortunately, not all CPUs have a write-through cache mode. So we
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* define PMAP_NEEDS_PTE_SYNC for C code to conditionally do PTE syncs,
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* and if there is the chance for PTE syncs to be needed, we define
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* PMAP_INCLUDE_PTE_SYNC so e.g. assembly code can include (and run)
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* the code.
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*/
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extern int pmap_needs_pte_sync;
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#if defined(_KERNEL_OPT)
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/*
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* StrongARM SA-1 caches do not have a write-through mode. So, on these,
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* we need to do PTE syncs. If only SA-1 is configured, then evaluate
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* this at compile time.
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*/
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#if (ARM_MMU_SA1 + ARM_MMU_V6 != 0) && (ARM_NMMUS == 1)
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#define PMAP_INCLUDE_PTE_SYNC
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#if (ARM_MMU_V6 > 0)
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#define PMAP_NEEDS_PTE_SYNC 1
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#elif (ARM_MMU_SA1 == 0)
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#define PMAP_NEEDS_PTE_SYNC 0
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#endif
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#endif
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#endif /* _KERNEL_OPT */
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/*
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* Provide a fallback in case we were not able to determine it at
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* compile-time.
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*/
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#ifndef PMAP_NEEDS_PTE_SYNC
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#define PMAP_NEEDS_PTE_SYNC pmap_needs_pte_sync
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#define PMAP_INCLUDE_PTE_SYNC
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#endif
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static inline void
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pmap_ptesync(pt_entry_t *ptep, size_t cnt)
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{
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if (PMAP_NEEDS_PTE_SYNC)
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cpu_dcache_wb_range((vaddr_t)ptep, cnt * sizeof(pt_entry_t));
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#if ARM_MMU_V7 > 0
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__asm("dsb");
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#endif
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}
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#define PTE_SYNC(ptep) pmap_ptesync((ptep), 1)
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#define PTE_SYNC_RANGE(ptep, cnt) pmap_ptesync((ptep), (cnt))
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#define l1pte_valid(pde) ((pde) != 0)
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#define l1pte_section_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_S)
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#define l1pte_supersection_p(pde) (l1pte_section_p(pde) \
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&& ((pde) & L1_S_V6_SUPER) != 0)
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#define l1pte_page_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_C)
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#define l1pte_fpage_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_F)
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#define l2pte_index(v) (((v) & L2_ADDR_BITS) >> L2_S_SHIFT)
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#define l2pte_valid(pte) (((pte) & L2_TYPE_MASK) != L2_TYPE_INV)
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#define l2pte_pa(pte) ((pte) & L2_S_FRAME)
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#define l2pte_minidata(pte) (((pte) & \
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(L2_B | L2_C | L2_XS_T_TEX(TEX_XSCALE_X)))\
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== (L2_C | L2_XS_T_TEX(TEX_XSCALE_X)))
|
|
|
|
/* L1 and L2 page table macros */
|
|
#define pmap_pde_v(pde) l1pte_valid(*(pde))
|
|
#define pmap_pde_section(pde) l1pte_section_p(*(pde))
|
|
#define pmap_pde_supersection(pde) l1pte_supersection_p(*(pde))
|
|
#define pmap_pde_page(pde) l1pte_page_p(*(pde))
|
|
#define pmap_pde_fpage(pde) l1pte_fpage_p(*(pde))
|
|
|
|
#define pmap_pte_v(pte) l2pte_valid(*(pte))
|
|
#define pmap_pte_pa(pte) l2pte_pa(*(pte))
|
|
|
|
/* Size of the kernel part of the L1 page table */
|
|
#define KERNEL_PD_SIZE \
|
|
(L1_TABLE_SIZE - (KERNEL_BASE >> L1_S_SHIFT) * sizeof(pd_entry_t))
|
|
|
|
/************************* ARM MMU configuration *****************************/
|
|
|
|
#if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0
|
|
void pmap_copy_page_generic(paddr_t, paddr_t);
|
|
void pmap_zero_page_generic(paddr_t);
|
|
|
|
void pmap_pte_init_generic(void);
|
|
#if defined(CPU_ARM8)
|
|
void pmap_pte_init_arm8(void);
|
|
#endif
|
|
#if defined(CPU_ARM9)
|
|
void pmap_pte_init_arm9(void);
|
|
#endif /* CPU_ARM9 */
|
|
#if defined(CPU_ARM10)
|
|
void pmap_pte_init_arm10(void);
|
|
#endif /* CPU_ARM10 */
|
|
#if defined(CPU_ARM11) /* ARM_MMU_V6 */
|
|
void pmap_pte_init_arm11(void);
|
|
#endif /* CPU_ARM11 */
|
|
#if defined(CPU_ARM11MPCORE) /* ARM_MMU_V6 */
|
|
void pmap_pte_init_arm11mpcore(void);
|
|
#endif
|
|
#if ARM_MMU_V7 == 1
|
|
void pmap_pte_init_armv7(void);
|
|
#endif /* ARM_MMU_V7 */
|
|
#endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */
|
|
|
|
#if ARM_MMU_SA1 == 1
|
|
void pmap_pte_init_sa1(void);
|
|
#endif /* ARM_MMU_SA1 == 1 */
|
|
|
|
#if ARM_MMU_XSCALE == 1
|
|
void pmap_copy_page_xscale(paddr_t, paddr_t);
|
|
void pmap_zero_page_xscale(paddr_t);
|
|
|
|
void pmap_pte_init_xscale(void);
|
|
|
|
void xscale_setup_minidata(vaddr_t, vaddr_t, paddr_t);
|
|
|
|
#define PMAP_UAREA(va) pmap_uarea(va)
|
|
void pmap_uarea(vaddr_t);
|
|
#endif /* ARM_MMU_XSCALE == 1 */
|
|
|
|
extern pt_entry_t pte_l1_s_cache_mode;
|
|
extern pt_entry_t pte_l1_s_cache_mask;
|
|
|
|
extern pt_entry_t pte_l2_l_cache_mode;
|
|
extern pt_entry_t pte_l2_l_cache_mask;
|
|
|
|
extern pt_entry_t pte_l2_s_cache_mode;
|
|
extern pt_entry_t pte_l2_s_cache_mask;
|
|
|
|
extern pt_entry_t pte_l1_s_cache_mode_pt;
|
|
extern pt_entry_t pte_l2_l_cache_mode_pt;
|
|
extern pt_entry_t pte_l2_s_cache_mode_pt;
|
|
|
|
extern pt_entry_t pte_l1_s_wc_mode;
|
|
extern pt_entry_t pte_l2_l_wc_mode;
|
|
extern pt_entry_t pte_l2_s_wc_mode;
|
|
|
|
extern pt_entry_t pte_l1_s_prot_u;
|
|
extern pt_entry_t pte_l1_s_prot_w;
|
|
extern pt_entry_t pte_l1_s_prot_ro;
|
|
extern pt_entry_t pte_l1_s_prot_mask;
|
|
|
|
extern pt_entry_t pte_l2_s_prot_u;
|
|
extern pt_entry_t pte_l2_s_prot_w;
|
|
extern pt_entry_t pte_l2_s_prot_ro;
|
|
extern pt_entry_t pte_l2_s_prot_mask;
|
|
|
|
extern pt_entry_t pte_l2_l_prot_u;
|
|
extern pt_entry_t pte_l2_l_prot_w;
|
|
extern pt_entry_t pte_l2_l_prot_ro;
|
|
extern pt_entry_t pte_l2_l_prot_mask;
|
|
|
|
extern pt_entry_t pte_l1_ss_proto;
|
|
extern pt_entry_t pte_l1_s_proto;
|
|
extern pt_entry_t pte_l1_c_proto;
|
|
extern pt_entry_t pte_l2_s_proto;
|
|
|
|
extern void (*pmap_copy_page_func)(paddr_t, paddr_t);
|
|
extern void (*pmap_zero_page_func)(paddr_t);
|
|
|
|
#endif /* !_LOCORE */
|
|
|
|
/*****************************************************************************/
|
|
|
|
/*
|
|
* Definitions for MMU domains
|
|
*/
|
|
#define PMAP_DOMAINS 15 /* 15 'user' domains (1-15) */
|
|
#define PMAP_DOMAIN_KERNEL 0 /* The kernel uses domain #0 */
|
|
|
|
/*
|
|
* These macros define the various bit masks in the PTE.
|
|
*
|
|
* We use these macros since we use different bits on different processor
|
|
* models.
|
|
*/
|
|
#define L1_S_PROT_U_generic (L1_S_AP(AP_U))
|
|
#define L1_S_PROT_W_generic (L1_S_AP(AP_W))
|
|
#define L1_S_PROT_RO_generic (0)
|
|
#define L1_S_PROT_MASK_generic (L1_S_PROT_U|L1_S_PROT_W|L1_S_PROT_RO)
|
|
|
|
#define L1_S_PROT_U_xscale (L1_S_AP(AP_U))
|
|
#define L1_S_PROT_W_xscale (L1_S_AP(AP_W))
|
|
#define L1_S_PROT_RO_xscale (0)
|
|
#define L1_S_PROT_MASK_xscale (L1_S_PROT_U|L1_S_PROT_W|L1_S_PROT_RO)
|
|
|
|
#define L1_S_PROT_U_armv6 (L1_S_AP(AP_R) | L1_S_AP(AP_U))
|
|
#define L1_S_PROT_W_armv6 (L1_S_AP(AP_W))
|
|
#define L1_S_PROT_RO_armv6 (L1_S_AP(AP_R) | L1_S_AP(AP_RO))
|
|
#define L1_S_PROT_MASK_armv6 (L1_S_PROT_U|L1_S_PROT_W|L1_S_PROT_RO)
|
|
|
|
#define L1_S_PROT_U_armv7 (L1_S_AP(AP_R) | L1_S_AP(AP_U))
|
|
#define L1_S_PROT_W_armv7 (L1_S_AP(AP_W))
|
|
#define L1_S_PROT_RO_armv7 (L1_S_AP(AP_R) | L1_S_AP(AP_RO))
|
|
#define L1_S_PROT_MASK_armv7 (L1_S_PROT_U|L1_S_PROT_W|L1_S_PROT_RO)
|
|
|
|
#define L1_S_CACHE_MASK_generic (L1_S_B|L1_S_C)
|
|
#define L1_S_CACHE_MASK_xscale (L1_S_B|L1_S_C|L1_S_XS_TEX(TEX_XSCALE_X))
|
|
#define L1_S_CACHE_MASK_armv6 (L1_S_B|L1_S_C|L1_S_XS_TEX(TEX_ARMV6_TEX))
|
|
#define L1_S_CACHE_MASK_armv7 (L1_S_B|L1_S_C|L1_S_XS_TEX(TEX_ARMV6_TEX)|L1_S_V6_S)
|
|
|
|
#define L2_L_PROT_U_generic (L2_AP(AP_U))
|
|
#define L2_L_PROT_W_generic (L2_AP(AP_W))
|
|
#define L2_L_PROT_RO_generic (0)
|
|
#define L2_L_PROT_MASK_generic (L2_L_PROT_U|L2_L_PROT_W|L2_L_PROT_RO)
|
|
|
|
#define L2_L_PROT_U_xscale (L2_AP(AP_U))
|
|
#define L2_L_PROT_W_xscale (L2_AP(AP_W))
|
|
#define L2_L_PROT_RO_xscale (0)
|
|
#define L2_L_PROT_MASK_xscale (L2_L_PROT_U|L2_L_PROT_W|L2_L_PROT_RO)
|
|
|
|
#define L2_L_PROT_U_armv6n (L2_AP0(AP_R) | L2_AP0(AP_U))
|
|
#define L2_L_PROT_W_armv6n (L2_AP0(AP_W))
|
|
#define L2_L_PROT_RO_armv6n (L2_AP0(AP_R) | L2_AP0(AP_RO))
|
|
#define L2_L_PROT_MASK_armv6n (L2_L_PROT_U|L2_L_PROT_W|L2_L_PROT_RO)
|
|
|
|
#define L2_L_PROT_U_armv7 (L2_AP0(AP_R) | L2_AP0(AP_U))
|
|
#define L2_L_PROT_W_armv7 (L2_AP0(AP_W))
|
|
#define L2_L_PROT_RO_armv7 (L2_AP0(AP_R) | L2_AP0(AP_RO))
|
|
#define L2_L_PROT_MASK_armv7 (L2_L_PROT_U|L2_L_PROT_W|L2_L_PROT_RO)
|
|
|
|
#define L2_L_CACHE_MASK_generic (L2_B|L2_C)
|
|
#define L2_L_CACHE_MASK_xscale (L2_B|L2_C|L2_XS_L_TEX(TEX_XSCALE_X))
|
|
#define L2_L_CACHE_MASK_armv6 (L2_B|L2_C|L2_V6_L_TEX(TEX_ARMV6_TEX))
|
|
#define L2_L_CACHE_MASK_armv7 (L2_B|L2_C|L2_V6_L_TEX(TEX_ARMV6_TEX)|L2_XS_S)
|
|
|
|
#define L2_S_PROT_U_generic (L2_AP(AP_U))
|
|
#define L2_S_PROT_W_generic (L2_AP(AP_W))
|
|
#define L2_S_PROT_RO_generic (0)
|
|
#define L2_S_PROT_MASK_generic (L2_S_PROT_U|L2_S_PROT_W|L2_S_PROT_RO)
|
|
|
|
#define L2_S_PROT_U_xscale (L2_AP0(AP_U))
|
|
#define L2_S_PROT_W_xscale (L2_AP0(AP_W))
|
|
#define L2_S_PROT_RO_xscale (0)
|
|
#define L2_S_PROT_MASK_xscale (L2_S_PROT_U|L2_S_PROT_W|L2_S_PROT_RO)
|
|
|
|
#define L2_S_PROT_U_armv6n (L2_AP0(AP_R) | L2_AP0(AP_U))
|
|
#define L2_S_PROT_W_armv6n (L2_AP0(AP_W))
|
|
#define L2_S_PROT_RO_armv6n (L2_AP0(AP_R) | L2_AP0(AP_RO))
|
|
#define L2_S_PROT_MASK_armv6n (L2_S_PROT_U|L2_S_PROT_W|L2_S_PROT_RO)
|
|
|
|
#define L2_S_PROT_U_armv7 (L2_AP0(AP_R) | L2_AP0(AP_U))
|
|
#define L2_S_PROT_W_armv7 (L2_AP0(AP_W))
|
|
#define L2_S_PROT_RO_armv7 (L2_AP0(AP_R) | L2_AP0(AP_RO))
|
|
#define L2_S_PROT_MASK_armv7 (L2_S_PROT_U|L2_S_PROT_W|L2_S_PROT_RO)
|
|
|
|
#define L2_S_CACHE_MASK_generic (L2_B|L2_C)
|
|
#define L2_S_CACHE_MASK_xscale (L2_B|L2_C|L2_XS_T_TEX(TEX_XSCALE_X))
|
|
#define L2_XS_CACHE_MASK_armv6 (L2_B|L2_C|L2_V6_XS_TEX(TEX_ARMV6_TEX))
|
|
#define L2_S_CACHE_MASK_armv6n L2_XS_CACHE_MASK_armv6
|
|
#ifdef ARMV6_EXTENDED_SMALL_PAGE
|
|
#define L2_S_CACHE_MASK_armv6c L2_XS_CACHE_MASK_armv6
|
|
#else
|
|
#define L2_S_CACHE_MASK_armv6c L2_S_CACHE_MASK_generic
|
|
#endif
|
|
#define L2_S_CACHE_MASK_armv7 (L2_B|L2_C|L2_V6_XS_TEX(TEX_ARMV6_TEX)|L2_XS_S)
|
|
|
|
|
|
#define L1_S_PROTO_generic (L1_TYPE_S | L1_S_IMP)
|
|
#define L1_S_PROTO_xscale (L1_TYPE_S)
|
|
#define L1_S_PROTO_armv6 (L1_TYPE_S)
|
|
#define L1_S_PROTO_armv7 (L1_TYPE_S)
|
|
|
|
#define L1_SS_PROTO_generic 0
|
|
#define L1_SS_PROTO_xscale 0
|
|
#define L1_SS_PROTO_armv6 (L1_TYPE_S | L1_S_V6_SS)
|
|
#define L1_SS_PROTO_armv7 (L1_TYPE_S | L1_S_V6_SS)
|
|
|
|
#define L1_C_PROTO_generic (L1_TYPE_C | L1_C_IMP2)
|
|
#define L1_C_PROTO_xscale (L1_TYPE_C)
|
|
#define L1_C_PROTO_armv6 (L1_TYPE_C)
|
|
#define L1_C_PROTO_armv7 (L1_TYPE_C)
|
|
|
|
#define L2_L_PROTO (L2_TYPE_L)
|
|
|
|
#define L2_S_PROTO_generic (L2_TYPE_S)
|
|
#define L2_S_PROTO_xscale (L2_TYPE_XS)
|
|
#ifdef ARMV6_EXTENDED_SMALL_PAGE
|
|
#define L2_S_PROTO_armv6c (L2_TYPE_XS) /* XP=0, extended small page */
|
|
#else
|
|
#define L2_S_PROTO_armv6c (L2_TYPE_S) /* XP=0, subpage APs */
|
|
#endif
|
|
#define L2_S_PROTO_armv6n (L2_TYPE_S) /* with XP=1 */
|
|
#define L2_S_PROTO_armv7 (L2_TYPE_S)
|
|
|
|
/*
|
|
* User-visible names for the ones that vary with MMU class.
|
|
*/
|
|
|
|
#if ARM_NMMUS > 1
|
|
/* More than one MMU class configured; use variables. */
|
|
#define L1_S_PROT_U pte_l1_s_prot_u
|
|
#define L1_S_PROT_W pte_l1_s_prot_w
|
|
#define L1_S_PROT_RO pte_l1_s_prot_ro
|
|
#define L1_S_PROT_MASK pte_l1_s_prot_mask
|
|
|
|
#define L2_S_PROT_U pte_l2_s_prot_u
|
|
#define L2_S_PROT_W pte_l2_s_prot_w
|
|
#define L2_S_PROT_RO pte_l2_s_prot_ro
|
|
#define L2_S_PROT_MASK pte_l2_s_prot_mask
|
|
|
|
#define L2_L_PROT_U pte_l2_l_prot_u
|
|
#define L2_L_PROT_W pte_l2_l_prot_w
|
|
#define L2_L_PROT_RO pte_l2_l_prot_ro
|
|
#define L2_L_PROT_MASK pte_l2_l_prot_mask
|
|
|
|
#define L1_S_CACHE_MASK pte_l1_s_cache_mask
|
|
#define L2_L_CACHE_MASK pte_l2_l_cache_mask
|
|
#define L2_S_CACHE_MASK pte_l2_s_cache_mask
|
|
|
|
#define L1_SS_PROTO pte_l1_ss_proto
|
|
#define L1_S_PROTO pte_l1_s_proto
|
|
#define L1_C_PROTO pte_l1_c_proto
|
|
#define L2_S_PROTO pte_l2_s_proto
|
|
|
|
#define pmap_copy_page(s, d) (*pmap_copy_page_func)((s), (d))
|
|
#define pmap_zero_page(d) (*pmap_zero_page_func)((d))
|
|
#elif (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0
|
|
#define L1_S_PROT_U L1_S_PROT_U_generic
|
|
#define L1_S_PROT_W L1_S_PROT_W_generic
|
|
#define L1_S_PROT_RO L1_S_PROT_RO_generic
|
|
#define L1_S_PROT_MASK L1_S_PROT_MASK_generic
|
|
|
|
#define L2_S_PROT_U L2_S_PROT_U_generic
|
|
#define L2_S_PROT_W L2_S_PROT_W_generic
|
|
#define L2_S_PROT_RO L2_S_PROT_RO_generic
|
|
#define L2_S_PROT_MASK L2_S_PROT_MASK_generic
|
|
|
|
#define L2_L_PROT_U L2_L_PROT_U_generic
|
|
#define L2_L_PROT_W L2_L_PROT_W_generic
|
|
#define L2_L_PROT_RO L2_L_PROT_RO_generic
|
|
#define L2_L_PROT_MASK L2_L_PROT_MASK_generic
|
|
|
|
#define L1_S_CACHE_MASK L1_S_CACHE_MASK_generic
|
|
#define L2_L_CACHE_MASK L2_L_CACHE_MASK_generic
|
|
#define L2_S_CACHE_MASK L2_S_CACHE_MASK_generic
|
|
|
|
#define L1_SS_PROTO L1_SS_PROTO_generic
|
|
#define L1_S_PROTO L1_S_PROTO_generic
|
|
#define L1_C_PROTO L1_C_PROTO_generic
|
|
#define L2_S_PROTO L2_S_PROTO_generic
|
|
|
|
#define pmap_copy_page(s, d) pmap_copy_page_generic((s), (d))
|
|
#define pmap_zero_page(d) pmap_zero_page_generic((d))
|
|
#elif ARM_MMU_V6N != 0
|
|
#define L1_S_PROT_U L1_S_PROT_U_armv6
|
|
#define L1_S_PROT_W L1_S_PROT_W_armv6
|
|
#define L1_S_PROT_RO L1_S_PROT_RO_armv6
|
|
#define L1_S_PROT_MASK L1_S_PROT_MASK_armv6
|
|
|
|
#define L2_S_PROT_U L2_S_PROT_U_armv6n
|
|
#define L2_S_PROT_W L2_S_PROT_W_armv6n
|
|
#define L2_S_PROT_RO L2_S_PROT_RO_armv6n
|
|
#define L2_S_PROT_MASK L2_S_PROT_MASK_armv6n
|
|
|
|
#define L2_L_PROT_U L2_L_PROT_U_armv6n
|
|
#define L2_L_PROT_W L2_L_PROT_W_armv6n
|
|
#define L2_L_PROT_RO L2_L_PROT_RO_armv6n
|
|
#define L2_L_PROT_MASK L2_L_PROT_MASK_armv6n
|
|
|
|
#define L1_S_CACHE_MASK L1_S_CACHE_MASK_armv6
|
|
#define L2_L_CACHE_MASK L2_L_CACHE_MASK_armv6
|
|
#define L2_S_CACHE_MASK L2_S_CACHE_MASK_armv6n
|
|
|
|
/* These prototypes make writeable mappings, while the other MMU types
|
|
* make read-only mappings. */
|
|
#define L1_SS_PROTO L1_SS_PROTO_armv6
|
|
#define L1_S_PROTO L1_S_PROTO_armv6
|
|
#define L1_C_PROTO L1_C_PROTO_armv6
|
|
#define L2_S_PROTO L2_S_PROTO_armv6n
|
|
|
|
#define pmap_copy_page(s, d) pmap_copy_page_generic((s), (d))
|
|
#define pmap_zero_page(d) pmap_zero_page_generic((d))
|
|
#elif ARM_MMU_V6C != 0
|
|
#define L1_S_PROT_U L1_S_PROT_U_generic
|
|
#define L1_S_PROT_W L1_S_PROT_W_generic
|
|
#define L1_S_PROT_RO L1_S_PROT_RO_generic
|
|
#define L1_S_PROT_MASK L1_S_PROT_MASK_generic
|
|
|
|
#define L2_S_PROT_U L2_S_PROT_U_generic
|
|
#define L2_S_PROT_W L2_S_PROT_W_generic
|
|
#define L2_S_PROT_RO L2_S_PROT_RO_generic
|
|
#define L2_S_PROT_MASK L2_S_PROT_MASK_generic
|
|
|
|
#define L2_L_PROT_U L2_L_PROT_U_generic
|
|
#define L2_L_PROT_W L2_L_PROT_W_generic
|
|
#define L2_L_PROT_RO L2_L_PROT_RO_generic
|
|
#define L2_L_PROT_MASK L2_L_PROT_MASK_generic
|
|
|
|
#define L1_S_CACHE_MASK L1_S_CACHE_MASK_generic
|
|
#define L2_L_CACHE_MASK L2_L_CACHE_MASK_generic
|
|
#define L2_S_CACHE_MASK L2_S_CACHE_MASK_generic
|
|
|
|
#define L1_SS_PROTO L1_SS_PROTO_generic
|
|
#define L1_S_PROTO L1_S_PROTO_generic
|
|
#define L1_C_PROTO L1_C_PROTO_generic
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#define L2_S_PROTO L2_S_PROTO_generic
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#define pmap_copy_page(s, d) pmap_copy_page_generic((s), (d))
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#define pmap_zero_page(d) pmap_zero_page_generic((d))
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#elif ARM_MMU_XSCALE == 1
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#define L1_S_PROT_U L1_S_PROT_U_generic
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#define L1_S_PROT_W L1_S_PROT_W_generic
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#define L1_S_PROT_RO L1_S_PROT_RO_generic
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#define L1_S_PROT_MASK L1_S_PROT_MASK_generic
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#define L2_S_PROT_U L2_S_PROT_U_xscale
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#define L2_S_PROT_W L2_S_PROT_W_xscale
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#define L2_S_PROT_RO L2_S_PROT_RO_xscale
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#define L2_S_PROT_MASK L2_S_PROT_MASK_xscale
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#define L2_L_PROT_U L2_L_PROT_U_generic
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#define L2_L_PROT_W L2_L_PROT_W_generic
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#define L2_L_PROT_RO L2_L_PROT_RO_generic
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#define L2_L_PROT_MASK L2_L_PROT_MASK_generic
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#define L1_S_CACHE_MASK L1_S_CACHE_MASK_xscale
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#define L2_L_CACHE_MASK L2_L_CACHE_MASK_xscale
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#define L2_S_CACHE_MASK L2_S_CACHE_MASK_xscale
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#define L1_SS_PROTO L1_SS_PROTO_xscale
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#define L1_S_PROTO L1_S_PROTO_xscale
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#define L1_C_PROTO L1_C_PROTO_xscale
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#define L2_S_PROTO L2_S_PROTO_xscale
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#define pmap_copy_page(s, d) pmap_copy_page_xscale((s), (d))
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#define pmap_zero_page(d) pmap_zero_page_xscale((d))
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#elif ARM_MMU_V7 == 1
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#define L1_S_PROT_U L1_S_PROT_U_armv7
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#define L1_S_PROT_W L1_S_PROT_W_armv7
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#define L1_S_PROT_RO L1_S_PROT_RO_armv7
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#define L1_S_PROT_MASK L1_S_PROT_MASK_armv7
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#define L2_S_PROT_U L2_S_PROT_U_armv7
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#define L2_S_PROT_W L2_S_PROT_W_armv7
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#define L2_S_PROT_RO L2_S_PROT_RO_armv7
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#define L2_S_PROT_MASK L2_S_PROT_MASK_armv7
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#define L2_L_PROT_U L2_L_PROT_U_armv7
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#define L2_L_PROT_W L2_L_PROT_W_armv7
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#define L2_L_PROT_RO L2_L_PROT_RO_armv7
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#define L2_L_PROT_MASK L2_L_PROT_MASK_armv7
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#define L1_S_CACHE_MASK L1_S_CACHE_MASK_armv7
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#define L2_L_CACHE_MASK L2_L_CACHE_MASK_armv7
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#define L2_S_CACHE_MASK L2_S_CACHE_MASK_armv7
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/* These prototypes make writeable mappings, while the other MMU types
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* make read-only mappings. */
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#define L1_SS_PROTO L1_SS_PROTO_armv7
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#define L1_S_PROTO L1_S_PROTO_armv7
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#define L1_C_PROTO L1_C_PROTO_armv7
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#define L2_S_PROTO L2_S_PROTO_armv7
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#define pmap_copy_page(s, d) pmap_copy_page_generic((s), (d))
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#define pmap_zero_page(d) pmap_zero_page_generic((d))
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#endif /* ARM_NMMUS > 1 */
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/*
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* Macros to set and query the write permission on page descriptors.
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*/
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#define l1pte_set_writable(pte) (((pte) & ~L1_S_PROT_RO) | L1_S_PROT_W)
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#define l1pte_set_readonly(pte) (((pte) & ~L1_S_PROT_W) | L1_S_PROT_RO)
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#define l2pte_set_writable(pte) (((pte) & ~L2_S_PROT_RO) | L2_S_PROT_W)
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#define l2pte_set_readonly(pte) (((pte) & ~L2_S_PROT_W) | L2_S_PROT_RO)
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#define l2pte_writable_p(pte) (((pte) & L2_S_PROT_W) == L2_S_PROT_W && \
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(L2_S_PROT_RO == 0 || \
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((pte) & L2_S_PROT_RO) != L2_S_PROT_RO))
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/*
|
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* These macros return various bits based on kernel/user and protection.
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* Note that the compiler will usually fold these at compile time.
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*/
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#define L1_S_PROT(ku, pr) ((((ku) == PTE_USER) ? L1_S_PROT_U : 0) | \
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(((pr) & VM_PROT_WRITE) ? L1_S_PROT_W : L1_S_PROT_RO))
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#define L2_L_PROT(ku, pr) ((((ku) == PTE_USER) ? L2_L_PROT_U : 0) | \
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(((pr) & VM_PROT_WRITE) ? L2_L_PROT_W : L2_L_PROT_RO))
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#define L2_S_PROT(ku, pr) ((((ku) == PTE_USER) ? L2_S_PROT_U : 0) | \
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(((pr) & VM_PROT_WRITE) ? L2_S_PROT_W : L2_S_PROT_RO))
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|
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/*
|
|
* Macros to test if a mapping is mappable with an L1 SuperSection,
|
|
* L1 Section, or an L2 Large Page mapping.
|
|
*/
|
|
#define L1_SS_MAPPABLE_P(va, pa, size) \
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((((va) | (pa)) & L1_SS_OFFSET) == 0 && (size) >= L1_SS_SIZE)
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|
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#define L1_S_MAPPABLE_P(va, pa, size) \
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((((va) | (pa)) & L1_S_OFFSET) == 0 && (size) >= L1_S_SIZE)
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|
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#define L2_L_MAPPABLE_P(va, pa, size) \
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((((va) | (pa)) & L2_L_OFFSET) == 0 && (size) >= L2_L_SIZE)
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|
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/*
|
|
* Hooks for the pool allocator.
|
|
*/
|
|
#define POOL_VTOPHYS(va) vtophys((vaddr_t) (va))
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|
|
#ifndef _LOCORE
|
|
|
|
/*
|
|
* pmap-specific data store in the vm_page structure.
|
|
*/
|
|
#define __HAVE_VM_PAGE_MD
|
|
struct vm_page_md {
|
|
SLIST_HEAD(,pv_entry) pvh_list; /* pv_entry list */
|
|
int pvh_attrs; /* page attributes */
|
|
u_int uro_mappings;
|
|
u_int urw_mappings;
|
|
union {
|
|
u_short s_mappings[2]; /* Assume kernel count <= 65535 */
|
|
u_int i_mappings;
|
|
} k_u;
|
|
#define kro_mappings k_u.s_mappings[0]
|
|
#define krw_mappings k_u.s_mappings[1]
|
|
#define k_mappings k_u.i_mappings
|
|
};
|
|
|
|
/*
|
|
* Set the default color of each page.
|
|
*/
|
|
#if ARM_MMU_V6 > 0
|
|
#define VM_MDPAGE_PVH_ATTRS_INIT(pg) \
|
|
(pg)->mdpage.pvh_attrs = (pg)->phys_addr & arm_cache_prefer_mask
|
|
#else
|
|
#define VM_MDPAGE_PVH_ATTRS_INIT(pg) \
|
|
(pg)->mdpage.pvh_attrs = 0
|
|
#endif
|
|
|
|
#define VM_MDPAGE_INIT(pg) \
|
|
do { \
|
|
SLIST_INIT(&(pg)->mdpage.pvh_list); \
|
|
VM_MDPAGE_PVH_ATTRS_INIT(pg); \
|
|
(pg)->mdpage.uro_mappings = 0; \
|
|
(pg)->mdpage.urw_mappings = 0; \
|
|
(pg)->mdpage.k_mappings = 0; \
|
|
} while (/*CONSTCOND*/0)
|
|
|
|
#endif /* !_LOCORE */
|
|
|
|
#endif /* _KERNEL */
|
|
|
|
#endif /* _ARM32_PMAP_H_ */
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