215 lines
8.3 KiB
C
215 lines
8.3 KiB
C
#include <net/gen/ether.h>
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#include <net/gen/eth_io.h>
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/* PCI STUFF */
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#define PCI_BASE_ADDRESS_0 0x10
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#define PCI_BASE_ADDRESS_1 0x14
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#define PCI_BASE_ADDRESS_2 0x18
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#define PCI_BASE_ADDRESS_3 0x1c
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#define PCI_BASE_ADDRESS_4 0x20
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#define PCI_BASE_ADDRESS_5 0x24
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#define PCI_BASE_ADDRESS_IO_MASK (~0x03)
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#define PCI_BASE_ADDRESS_SPACE_IO 0x01
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#define PCI_INTERRUPT_LINE 0x3c
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#define PCI_INTERRUPT_PIN 0x3d
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#define PCI_COMMAND_MASTER 0x4
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#define PCI_VENDOR_ID_AMD 0x1022
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#define PCI_DEVICE_ID_AMD_LANCE 0x2000
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/* supported max number of ether cards */
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#define EC_PORT_NR_MAX 2
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/* macros for 'mode' */
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#define EC_DISABLED 0x0
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#define EC_SINK 0x1
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#define EC_ENABLED 0x2
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/* macros for 'flags' */
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#define ECF_EMPTY 0x000
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#define ECF_PACK_SEND 0x001
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#define ECF_PACK_RECV 0x002
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#define ECF_SEND_AVAIL 0x004
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#define ECF_READING 0x010
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#define ECF_PROMISC 0x040
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#define ECF_MULTI 0x080
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#define ECF_BROAD 0x100
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#define ECF_ENABLED 0x200
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#define ECF_STOPPED 0x400
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/* === macros for ether cards (our generalized version) === */
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#define EC_ISR_RINT 0x0001
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#define EC_ISR_WINT 0x0002
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#define EC_ISR_RERR 0x0010
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#define EC_ISR_WERR 0x0020
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#define EC_ISR_ERR 0x0040
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#define EC_ISR_RST 0x0100
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/* IOVEC */
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#define IOVEC_NR 16
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typedef struct iovec_dat
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{
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iovec_s_t iod_iovec[IOVEC_NR];
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int iod_iovec_s;
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int iod_proc_nr;
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cp_grant_id_t iod_grant;
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vir_bytes iod_iovec_offset;
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} iovec_dat_t;
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#define ETH0_SELECTOR 0x61
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#define ETH1_SELECTOR 0x69
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/* ====== ethernet card info. ====== */
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typedef struct ether_card
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{
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/* ####### MINIX style ####### */
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char port_name[sizeof("eth_card#n")];
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int flags;
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int mode;
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int transfer_mode;
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eth_stat_t eth_stat;
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iovec_dat_t read_iovec;
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iovec_dat_t write_iovec;
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iovec_dat_t tmp_iovec;
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vir_bytes write_s;
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vir_bytes read_s;
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int client;
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message sendmsg;
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/* ######## device info. ####### */
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port_t ec_port;
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phys_bytes ec_linmem;
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int ec_irq;
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int ec_int_pending;
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int ec_hook;
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int ec_ramsize;
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/* PCI */
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u8_t ec_pcibus;
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u8_t ec_pcidev;
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u8_t ec_pcifunc;
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/* Addrassing */
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u16_t ec_memseg;
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vir_bytes ec_memoff;
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ether_addr_t mac_address;
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} ether_card_t;
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#define DEI_DEFAULT 0x8000
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/*
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* NOTE: Not all the CSRs are defined. Just the ones that were deemed
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* necessary or potentially useful.
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*/
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/* Control and Status Register Addresses */
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#define LANCE_CSR0 0 /* Controller Status Register */
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#define LANCE_CSR1 1 /* Initialization Block Address (Lower) */
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#define LANCE_CSR2 2 /* Initialization Block Address (Upper) */
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#define LANCE_CSR3 3 /* Interrupt Masks and Deferral Control */
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#define LANCE_CSR4 4 /* Test and Features Control */
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#define LANCE_CSR5 5 /* Extended Control and Interrupt */
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#define LANCE_CSR8 8 /* Logical Address Filter 0 */
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#define LANCE_CSR9 9 /* Logical Address Filter 1 */
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#define LANCE_CSR10 10 /* Logical Address Filter 2 */
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#define LANCE_CSR11 11 /* Logical Address Filter 3 */
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#define LANCE_CSR15 15 /* Mode */
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#define LANCE_CSR88 88 /* Chip ID Register (Lower) */
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#define LANCE_CSR89 89 /* Chip ID Register (Upper) */
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/* Control and Status Register 0 (CSR0) */
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#define LANCE_CSR0_ERR 0x8000 /* Error Occurred */
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#define LANCE_CSR0_BABL 0x4000 /* Transmitter Timeout Error */
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#define LANCE_CSR0_CERR 0x2000 /* Collision Error */
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#define LANCE_CSR0_MISS 0x1000 /* Missed Frame */
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#define LANCE_CSR0_MERR 0x0800 /* Memory Error */
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#define LANCE_CSR0_RINT 0x0400 /* Receive Interrupt */
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#define LANCE_CSR0_TINT 0x0200 /* Transmit Interrupt */
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#define LANCE_CSR0_IDON 0x0100 /* Initialization Done */
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#define LANCE_CSR0_INTR 0x0080 /* Interrupt Flag */
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#define LANCE_CSR0_IENA 0x0040 /* Interrupt Enable */
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#define LANCE_CSR0_RXON 0x0020 /* Receive On */
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#define LANCE_CSR0_TXON 0x0010 /* Transmit On */
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#define LANCE_CSR0_TDMD 0x0008 /* Transmit Demand */
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#define LANCE_CSR0_STOP 0x0004 /* Stop */
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#define LANCE_CSR0_STRT 0x0002 /* Start */
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#define LANCE_CSR0_INIT 0x0001 /* Init */
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/* Control and Status Register 3 (CSR3) */
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/* 0x8000 Reserved */
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#define LANCE_CSR3_BABLM 0x4000 /* Babble Mask */
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/* 0x2000 Reserved */
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#define LANCE_CSR3_MISSM 0x1000 /* Missed Frame Mask */
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#define LANCE_CSR3_MERRM 0x0800 /* Memory Error Mask */
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#define LANCE_CSR3_RINTM 0x0400 /* Receive Interrupt Mask */
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#define LANCE_CSR3_TINTM 0x0200 /* Transmit Interrupt Mask */
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#define LANCE_CSR3_IDONM 0x0100 /* Initialization Done Mask */
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/* 0x0080 Reserved */
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#define LANCE_CSR3_DXSUFLO 0x0040 /* Disable Transmit Stop on Underflow */
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#define LANCE_CSR3_LAPPEN 0x0020 /* Look Ahead Packet Processing Enable */
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#define LANCE_CSR3_DXMT2PD 0x0010 /* Disable Transmit Two Part Deferral */
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#define LANCE_CSR3_EMBA 0x0008 /* Enable Modified Back-off Algorithm */
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#define LANCE_CSR3_BSWP 0x0004 /* Byte Swap */
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/* 0x0002 Reserved
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* 0x0001 Reserved */
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/* Control and Status Register 4 (CSR4) */
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#define LANCE_CSR4_EN124 0x8000 /* Enable CSR124 Access */
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#define LANCE_CSR4_DMAPLUS 0x4000 /* Disable DMA Burst Transfer Counter */
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#define LANCE_CSR4_TIMER 0x2000 /* Enable Bus Activity Timer */
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#define LANCE_CSR4_DPOLL 0x1000 /* Disable Transmit Polling */
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#define LANCE_CSR4_APAD_XMT 0x0800 /* Auto Pad Transmit */
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#define LANCE_CSR4_ASTRP_RCV 0x0400 /* Auto Strip Receive */
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#define LANCE_CSR4_MFCO 0x0200 /* Missed Frame Counter Overflow */
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#define LANCE_CSR4_MFCOM 0x0100 /* Missed Frame Counter Overflow Mask */
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#define LANCE_CSR4_UINTCMD 0x0080 /* User Interrupt Command */
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#define LANCE_CSR4_UINT 0x0040 /* User Interrupt */
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#define LANCE_CSR4_RCVCCO 0x0020 /* Receive Collision Counter Overflow */
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#define LANCE_CSR4_RCVCCOM 0x0010 /* Receive Collision Counter Overflow
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* Mask */
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#define LANCE_CSR4_TXSTRT 0x0008 /* Transmit Start */
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#define LANCE_CSR4_TXSTRTM 0x0004 /* Transmit Start Mask */
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#define LANCE_CSR4_JAB 0x0002 /* Jabber Error */
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#define LANCE_CSR4_JABM 0x0001 /* Jabber Error Mask */
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/* Control and Status Register 5 (CSR5) */
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#define LANCE_CSR5_TOKINTD 0x8000 /* Transmit OK Interrupt Disable */
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#define LANCE_CSR5_LINTEN 0x4000 /* Last Transmit Interrupt Enable */
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/* 0x2000 Reserved
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* 0x1000 Reserved */
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#define LANCE_CSR5_SINT 0x0800 /* System Interrupt */
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#define LANCE_CSR5_SINTE 0x0400 /* System Interrupt Enable */
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#define LANCE_CSR5_SLPINT 0x0200 /* Sleep Interrupt */
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#define LANCE_CSR5_SLPINTE 0x0100 /* Sleep Interrupt Enable */
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#define LANCE_CSR5_EXDINT 0x0080 /* Excessive Deferral Interrupt */
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#define LANCE_CSR5_EXDINTE 0x0040 /* Excessive Deferral Interrupt Enable */
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#define LANCE_CSR5_MPPLBA 0x0020 /* Magic Packet Physical Logical Broadcast
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* Accept */
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#define LANCE_CSR5_MPINT 0x0010 /* Magic Packet Interrupt */
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#define LANCE_CSR5_MPINTE 0x0008 /* Magic Packet Interrupt Enable */
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#define LANCE_CSR5_MPEN 0x0004 /* Magic Packet Enable */
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#define LANCE_CSR5_MPMODE 0x0002 /* Magic Packet Mode */
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#define LANCE_CSR5_SPND 0x0001 /* Suspend */
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/* Control and Status Register 15 (CSR15) */
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#define LANCE_CSR15_PROM 0x8000 /* Promiscuous Mode */
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#define LANCE_CSR15_DRCVBC 0x4000 /* Disable Receive Broadcast */
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#define LANCE_CSR15_DRCVPA 0x2000 /* Disable Receive Physical Address */
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#define LANCE_CSR15_DLNKTST 0x1000 /* Disable Link Status */
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#define LANCE_CSR15_DAPC 0x0800 /* Disable Automatic Polarity Correction */
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#define LANCE_CSR15_MENDECL 0x0400 /* MENDEC Loopback Mode */
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#define LANCE_CSR15_LRT 0x0200 /* Low Receive Threshold (T-MAU Mode) */
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#define LANCE_CSR15_TSEL 0x0200 /* Transmit Mode Select (AUI Mode) */
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/* 0x0100 Portsel[1]
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* 0x0080 Portsel[0] */
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#define LANCE_CSR15_INTL 0x0040 /* Internal Loopback */
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#define LANCE_CSR15_DRTY 0x0020 /* Disable Retry */
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#define LANCE_CSR15_FCOLL 0x0010 /* Force Collision */
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#define LANCE_CSR15_DXMTFCS 0x0008 /* Disable Transmit CRC (FCS) */
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#define LANCE_CSR15_LOOP 0x0004 /* Loopback Enable */
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#define LANCE_CSR15_DTX 0x0002 /* Disable Transmit */
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#define LANCE_CSR15_DRX 0x0001 /* Disable Receiver */
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