84d9c625bf
- Fix for possible unset uid/gid in toproto
- Fix for default mtree style
- Update libelf
- Importing libexecinfo
- Resynchronize GCC, mpc, gmp, mpfr
- build.sh: Replace params with show-params.
This has been done as the make target has been renamed in the same
way, while a new target named params has been added. This new
target generates a file containing all the parameters, instead of
printing it on the console.
- Update test48 with new etc/services (Fix by Ben Gras <ben@minix3.org)
get getservbyport() out of the inner loop
Change-Id: Ie6ad5226fa2621ff9f0dee8782ea48f9443d2091
267 lines
5.8 KiB
ArmAsm
267 lines
5.8 KiB
ArmAsm
/*-
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* Copyright (c) 2013 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Matt Thomas of 3am Software Foundry.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arm/asm.h>
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#include <arm/vfpreg.h>
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RCSID("$NetBSD: vfpsf.S,v 1.2 2013/06/23 06:19:55 matt Exp $")
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/*
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* This file provides softfloat compatible routines which use VFP instructions
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* to do the actual work. This should give near hard-float performance while
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* being compatible with soft-float code.
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*
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* This file implements the single precision floating point routines.
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*/
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#ifdef __ARM_EABI__
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#define __addsf3 __aeabi_fadd
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#define __divsf3 __aeabi_fdiv
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#define __mulsf3 __aeabi_fmul
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#define __subsf3 __aeabi_fsub
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#define __negsf2 __aeabi_fneg
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#define __truncdfsf2 __aeabi_d2f
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#define __fixsfsi __aeabi_f2iz
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#define __fixunssfsi __aeabi_f2uiz
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#define __floatsisf __aeabi_i2f
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#define __floatunsisf __aeabi_ui2f
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#endif
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ENTRY(__addsf3)
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vmov s0, s1, r0, r1
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vadd.f32 s0, s0, s1
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vmov r0, s0
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RET
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END(__addsf3)
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ENTRY(__subsf3)
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vmov s0, s1, r0, r1
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vsub.f32 s0, s0, s1
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vmov r0, s0
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RET
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END(__subsf3)
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#ifdef __ARM_EABI__
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ENTRY(__aeabi_frsub)
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vmov s0, s1, r0, r1
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vsub.f32 s0, s1, s0
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vmov r0, s0
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RET
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END(__aeabi_frsub)
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#endif
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ENTRY(__mulsf3)
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vmov s0, s1, r0, r1
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vmul.f32 s0, s0, s1
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vmov r0, s0
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RET
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END(__mulsf3)
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ENTRY(__divsf3)
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vmov s0, s1, r0, r1
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vdiv.f32 s0, s0, s1
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vmov r0, s0
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RET
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END(__divsf3)
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ENTRY(__negsf2)
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vmov s0, r0
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vneg.f32 s0, s0
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vmov r0, s0
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RET
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END(__negsf2)
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ENTRY(__truncdfsf2)
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#ifdef __ARMEL__
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vmov d0, r0, r1
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#else
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vmov d0, r1, r0
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#endif
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vcvt.f32.f64 s0, d0
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vmov r0, s0
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RET
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END(__truncdfsf2)
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ENTRY(__fixsfsi)
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vmov s0, r0
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vcvt.s32.f32 s0, s0
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vmov r0, s0
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RET
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END(__fixsfsi)
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ENTRY(__fixunssfsi)
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vmov s0, r0
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vcvt.u32.f32 s0, s0
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vmov r0, s0
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RET
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END(__fixunssfsi)
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ENTRY(__floatsisf)
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vmov s0, r0
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vcvt.f32.s32 s0, s0
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vmov r0, s0
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RET
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END(__floatsisf)
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ENTRY(__floatunsisf)
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vmov s0, r0
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vcvt.f32.u32 s0, s0
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vmov r0, s0
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RET
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END(__floatunsisf)
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/*
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* Effect of a floating point comparision on the condition flags.
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* N Z C V
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* EQ = 0 1 1 0
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* LT = 1 0 0 0
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* GT = 0 0 1 0
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* UN = 0 0 1 1
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*/
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#ifdef __ARM_EABI__
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ENTRY(__aeabi_cfcmpeq)
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vmov s0, s1, r0, r1
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vcmp.f32 s0, s1
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vmrs APSR_nzcv, fpscr
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RET
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END(__aeabi_cfcmpeq)
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ENTRY(__aeabi_cfcmple)
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vmov s0, s1, r0, r1
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vcmpe.f32 s0, s1
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vmrs APSR_nzcv, fpscr
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RET
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END(__aeabi_cfcmple)
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ENTRY(__aeabi_cfrcmple)
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vmov s0, s1, r0, r1
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vcmpe.f32 s1, s0
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vmrs APSR_nzcv, fpscr
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RET
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END(__aeabi_cfrcmple)
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ENTRY(__aeabi_fcmpeq)
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vmov s0, s1, r0, r1
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vcmp.f32 s0, s1
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vmrs APSR_nzcv, fpscr
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moveq r0, #1 /* (a == b) */
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movne r0, #0 /* (a != b) or unordered */
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RET
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END(__aeabi_fcmpeq)
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ENTRY(__aeabi_fcmplt)
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vmov s0, s1, r0, r1
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vcmp.f32 s0, s1
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vmrs APSR_nzcv, fpscr
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movlt r0, #1 /* (a < b) */
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movcs r0, #0 /* (a >= b) or unordered */
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RET
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END(__aeabi_fcmplt)
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ENTRY(__aeabi_fcmple)
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vmov s0, s1, r0, r1
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vcmp.f32 s0, s1
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vmrs APSR_nzcv, fpscr
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movls r0, #1 /* (a <= b) */
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movhi r0, #0 /* (a > b) or unordered */
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RET
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END(__aeabi_fcmple)
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ENTRY(__aeabi_fcmpge)
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vmov s0, s1, r0, r1
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vcmp.f32 s0, s1
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vmrs APSR_nzcv, fpscr
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movge r0, #1 /* (a >= b) */
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movlt r0, #0 /* (a < b) or unordered */
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RET
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END(__aeabi_fcmpge)
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ENTRY(__aeabi_fcmpgt)
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vmov s0, s1, r0, r1
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vcmp.f32 s0, s1
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vmrs APSR_nzcv, fpscr
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movgt r0, #1 /* (a > b) */
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movle r0, #0 /* (a <= b) or unordered */
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RET
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END(__aeabi_fcmpgt)
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ENTRY(__aeabi_fcmpun)
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vmov s0, s1, r0, r1
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vcmp.f32 s0, s1
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vmrs APSR_nzcv, fpscr
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movvs r0, #1 /* (isnan(a) || isnan(b)) */
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movvc r0, #0 /* !isnan(a) && !isnan(b) */
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RET
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END(__aeabi_fcmpun)
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#else
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/* N set if compare <= result */
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/* Z set if compare = result */
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/* C set if compare (=,>=,UNORD) result */
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/* V set if compare UNORD result */
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STRONG_ALIAS(__eqsf2, __nesf2)
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ENTRY(__nesf2)
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vmov s0, s1, r0, r1
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vcmp.f32 s0, s1
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vmrs APSR_nzcv, fpscr
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moveq r0, #0 /* !(a == b) */
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movne r0, #1 /* !(a == b) */
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RET
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END(__nesf2)
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STRONG_ALIAS(__gesf2, __ltsf2)
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ENTRY(__ltsf2)
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vmov s0, s1, r0, r1
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vcmp.f32 s0, s1
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vmrs APSR_nzcv, fpscr
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mvnmi r0, #0 /* -(a < b) */
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movpl r0, #0 /* -(a < b) */
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RET
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END(__ltsf2)
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STRONG_ALIAS(__gtsf2, __lesf2)
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ENTRY(__lesf2)
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vmov s0, s1, r0, r1
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vcmp.f32 s0, s1
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vmrs APSR_nzcv, fpscr
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movgt r0, #1 /* (a > b) */
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movle r0, #0 /* (a > b) */
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RET
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END(__lesf2)
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ENTRY(__unordsf2)
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vmov s0, s1, r0, r1
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vcmp.f32 s0, s1
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vmrs APSR_nzcv, fpscr
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movvs r0, #1 /* isnan(a) || isnan(b) */
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movvc r0, #0 /* isnan(a) || isnan(b) */
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RET
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END(__unordsf2)
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#endif /* !__ARM_EABI__ */
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