2d64210c1d
Written by JP Embedded. Host controller (HCD), mass storage, and hub drivers. Change-Id: I4237cf7aeb4a1c0205a1876593a9cc67ef3d577e
191 lines
7 KiB
C
191 lines
7 KiB
C
/*
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* Common MUSB core registers definitions
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*/
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#ifndef _MUSB_REGS_H_
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#define _MUSB_REGS_H_
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#include <usbd/hcd_common.h>
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/*===========================================================================*
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* MUSB core register offsets *
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*===========================================================================*/
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#define MUSB_REG_FADDR 0x00u
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#define MUSB_REG_POWER 0x01u
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#define MUSB_REG_INTRTX 0x02u
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#define MUSB_REG_INTRRX 0x04u
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#define MUSB_REG_INTRTXE 0x06u
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#define MUSB_REG_INTRRXE 0x08u
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#define MUSB_REG_INTRUSB 0x0Au
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#define MUSB_REG_INTRUSBE 0x0Bu
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#define MUSB_REG_FRAME 0x0Cu
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#define MUSB_REG_INDEX 0x0Eu
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#define MUSB_REG_TESTMODE 0x0Fu
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/* Proxy registers for endpoint configuration,
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* that correspond to specific endpoint's register space
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* selected with MUSB_REG_INDEX */
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#define MUSB_REG_TXMAXP 0x10u
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#define MUSB_REG_PERI_CSR0 0x12u
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#define MUSB_REG_HOST_CSR0 MUSB_REG_PERI_CSR0
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#define MUSB_REG_PERI_TXCSR MUSB_REG_PERI_CSR0
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#define MUSB_REG_HOST_TXCSR MUSB_REG_PERI_CSR0
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#define MUSB_REG_RXMAXP 0x14u
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#define MUSB_REG_PERI_RXCSR 0x16u
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#define MUSB_REG_HOST_RXCSR MUSB_REG_PERI_RXCSR
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#define MUSB_REG_COUNT0 0x18u
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#define MUSB_REG_RXCOUNT MUSB_REG_COUNT0
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#define MUSB_REG_HOST_TYPE0 0x1Au
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#define MUSB_REG_HOST_TXTYPE MUSB_REG_HOST_TYPE0
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#define MUSB_REG_HOST_NAKLIMIT0 0x1Bu
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#define MUSB_REG_HOST_TXINTERVAL MUSB_REG_HOST_NAKLIMIT0
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#define MUSB_REG_HOST_RXTYPE 0x1Cu
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#define MUSB_REG_HOST_RXINTERVAL 0x1Du
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#define MUSB_REG_FIFO0 0x20u
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#define MUSB_REG_FIFO1 0x24u
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#define MUSB_REG_FIFO2 0x28u
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#define MUSB_REG_FIFO3 0x2Cu
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#define MUSB_REG_FIFO4 0x30u
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#define MUSB_REG_FIFO_LEN 0x04u
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#define MUSB_REG_DEVCTL 0x60u
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#define MUSB_REG_TXFIFOSZ 0x62u
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#define MUSB_REG_RXFIFOSZ 0x63u
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#define MUSB_REG_TXFIFOADDR 0x64u
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#define MUSB_REG_RXFIFOADDR 0x66u
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#define MUSB_REG_EP_CONFIG_BASE 0x80u
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#define MUSB_REG_TXFUNCADDR 0x00u
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#define MUSB_REG_TXHUBADDR 0x02u
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#define MUSB_REG_TXHUBPORT 0x03u
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#define MUSB_REG_RXFUNCADDR 0x04u
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#define MUSB_REG_RXHUBADDR 0x06u
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#define MUSB_REG_RXHUBPORT 0x07u
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#define MUSB_REG_EP_CONFIG_LEN 0x08u
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#define MUSB_REG_CONFIG(ep,reg) \
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(MUSB_REG_EP_CONFIG_BASE + (MUSB_REG_EP_CONFIG_LEN * (ep)) + (reg))
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/*===========================================================================*
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* MUSB core register values *
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*===========================================================================*/
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/* POWER */
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#define MUSB_VAL_POWER_ENSUSPM HCD_BIT(0)
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#define MUSB_VAL_POWER_SUSPENDM HCD_BIT(1)
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#define MUSB_VAL_POWER_RESUME HCD_BIT(2)
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#define MUSB_VAL_POWER_RESET HCD_BIT(3)
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#define MUSB_VAL_POWER_HSMODE HCD_BIT(4)
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#define MUSB_VAL_POWER_HSEN HCD_BIT(5)
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#define MUSB_VAL_POWER_SOFTCONN HCD_BIT(6)
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#define MUSB_VAL_POWER_ISOUPDATE HCD_BIT(7)
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/* DEVCTL */
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#define MUSB_VAL_DEVCTL_SESSION HCD_BIT(0)
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#define MUSB_VAL_DEVCTL_HOSTREQ HCD_BIT(1)
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#define MUSB_VAL_DEVCTL_HOSTMODE HCD_BIT(2)
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#define MUSB_VAL_DEVCTL_VBUS_1 HCD_BIT(3)
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#define MUSB_VAL_DEVCTL_VBUS_2 HCD_BIT(4)
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#define MUSB_VAL_DEVCTL_VBUS_3 (HCD_BIT(3) | HCD_BIT(4))
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#define MUSB_VAL_DEVCTL_LSDEV HCD_BIT(5)
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#define MUSB_VAL_DEVCTL_FSDEV HCD_BIT(6)
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#define MUSB_VAL_DEVCTL_BDEVICE HCD_BIT(7)
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/* INTRUSBE */
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#define MUSB_VAL_INTRUSBE_SUSPEND HCD_BIT(0)
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#define MUSB_VAL_INTRUSBE_RESUME HCD_BIT(1)
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#define MUSB_VAL_INTRUSBE_RESET_BABBLE HCD_BIT(2)
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#define MUSB_VAL_INTRUSBE_SOF HCD_BIT(3)
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#define MUSB_VAL_INTRUSBE_CONN HCD_BIT(4)
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#define MUSB_VAL_INTRUSBE_DISCON HCD_BIT(5)
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#define MUSB_VAL_INTRUSBE_SESSREQ HCD_BIT(6)
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#define MUSB_VAL_INTRUSBE_VBUSERR HCD_BIT(7)
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#define MUSB_VAL_INTRUSBE_NONE 0x00u
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/* HOST_TYPE0 */
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#define MUSB_VAL_HOST_TYPE0_MASK (HCD_BIT(6) | HCD_BIT(7))
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#define MUSB_VAL_HOST_TYPE0_HIGH_SPEED HCD_BIT(6)
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#define MUSB_VAL_HOST_TYPE0_FULL_SPEED HCD_BIT(7)
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#define MUSB_VAL_HOST_TYPE0_LOW_SPEED (HCD_BIT(6) | HCD_BIT(7))
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/* INTRTXE */
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#define MUSB_VAL_INTRTXE_EP0 HCD_BIT(0)
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#define MUSB_VAL_INTRTXE_EP1TX HCD_BIT(1)
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#define MUSB_VAL_INTRTXE_EP2TX HCD_BIT(2)
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#define MUSB_VAL_INTRTXE_EP3TX HCD_BIT(3)
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#define MUSB_VAL_INTRTXE_EP4TX HCD_BIT(4)
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/* HOST_CSR0 */
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#define MUSB_VAL_HOST_CSR0_RXPKTRDY HCD_BIT(0)
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#define MUSB_VAL_HOST_CSR0_TXPKTRDY HCD_BIT(1)
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#define MUSB_VAL_HOST_CSR0_RXSTALL HCD_BIT(2)
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#define MUSB_VAL_HOST_CSR0_SETUPPKT HCD_BIT(3)
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#define MUSB_VAL_HOST_CSR0_ERROR HCD_BIT(4)
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#define MUSB_VAL_HOST_CSR0_REQPKT HCD_BIT(5)
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#define MUSB_VAL_HOST_CSR0_STATUSPKT HCD_BIT(6)
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#define MUSB_VAL_HOST_CSR0_NAK_TIMEOUT HCD_BIT(7)
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#define MUSB_VAL_HOST_CSR0_FLUSHFIFO HCD_BIT(8)
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/* HOST_RXTYPE/HOST_TXTYPE */
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#define MUSB_VAL_HOST_XXTYPE_SPEED_MASK (HCD_BIT(6) | HCD_BIT(7))
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#define MUSB_VAL_HOST_XXTYPE_HIGH_SPEED HCD_BIT(6)
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#define MUSB_VAL_HOST_XXTYPE_FULL_SPEED HCD_BIT(7)
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#define MUSB_VAL_HOST_XXTYPE_LOW_SPEED (HCD_BIT(6) | HCD_BIT(7))
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#define MUSB_VAL_HOST_XXTYPE_PROT_MASK (HCD_BIT(4) | HCD_BIT(5))
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#define MUSB_VAL_HOST_XXTYPE_ISOCHRONOUS HCD_BIT(4)
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#define MUSB_VAL_HOST_XXTYPE_BULK HCD_BIT(5)
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#define MUSB_VAL_HOST_XXTYPE_INTERRUPT (HCD_BIT(4) | HCD_BIT(5))
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#define MUSB_VAL_HOST_XXTYPE_RENDPN_MASK (HCD_BIT(0) | \
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HCD_BIT(1) | \
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HCD_BIT(2) | \
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HCD_BIT(3))
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/* HOST_RXCSR */
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#define MUSB_VAL_HOST_RXCSR_RXPKTRDY HCD_BIT(0)
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#define MUSB_VAL_HOST_RXCSR_FIFOFULL HCD_BIT(1)
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#define MUSB_VAL_HOST_RXCSR_ERROR HCD_BIT(2)
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#define MUSB_VAL_HOST_RXCSR_NAKTIMEOUT HCD_BIT(3)
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#define MUSB_VAL_HOST_RXCSR_FLUSHFIFO HCD_BIT(4)
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#define MUSB_VAL_HOST_RXCSR_REQPKT HCD_BIT(5)
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#define MUSB_VAL_HOST_RXCSR_RXSTALL HCD_BIT(6)
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#define MUSB_VAL_HOST_RXCSR_CLRDATATOG HCD_BIT(7)
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#define MUSB_VAL_HOST_RXCSR_DATATOG HCD_BIT(9)
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#define MUSB_VAL_HOST_RXCSR_DATATOGWREN HCD_BIT(10)
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#define MUSB_VAL_HOST_RXCSR_DISNYET HCD_BIT(12)
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#define MUSB_VAL_HOST_RXCSR_DMAEN HCD_BIT(13)
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/* HOST_TXCSR */
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#define MUSB_VAL_HOST_TXCSR_TXPKTRDY HCD_BIT(0)
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#define MUSB_VAL_HOST_TXCSR_FIFONOTEMPTY HCD_BIT(1)
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#define MUSB_VAL_HOST_TXCSR_ERROR HCD_BIT(2)
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#define MUSB_VAL_HOST_TXCSR_FLUSHFIFO HCD_BIT(3)
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#define MUSB_VAL_HOST_TXCSR_SETUPPKT HCD_BIT(4)
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#define MUSB_VAL_HOST_TXCSR_RXSTALL HCD_BIT(5)
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#define MUSB_VAL_HOST_TXCSR_CLRDATATOG HCD_BIT(6)
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#define MUSB_VAL_HOST_TXCSR_NAK_TIMEOUT HCD_BIT(7)
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#define MUSB_VAL_HOST_TXCSR_DATATOG HCD_BIT(8)
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#define MUSB_VAL_HOST_TXCSR_DATATOGWREN HCD_BIT(9)
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#define MUSB_VAL_HOST_TXCSR_DMAMODE HCD_BIT(10)
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#define MUSB_VAL_HOST_TXCSR_FRCDATATOG HCD_BIT(11)
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#define MUSB_VAL_HOST_TXCSR_DMAEN HCD_BIT(12)
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#define MUSB_VAL_HOST_TXCSR_MODE HCD_BIT(13)
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#define MUSB_VAL_HOST_TXCSR_ISO HCD_BIT(14)
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#define MUSB_VAL_HOST_TXCSR_AUTOSET HCD_BIT(15)
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/* RXFIFOADDR/TXFIFOADDR */
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#define MUSB_VAL_XXFIFOADDR_EP0_END 0x08u
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/* RXFIFOSZ/TXFIFOSZ */
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#define MUSB_VAL_XXFIFOSZ_16 0x01u
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#define MUSB_VAL_XXFIFOSZ_32 0x02u
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#define MUSB_VAL_XXFIFOSZ_64 0x03u
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#define MUSB_VAL_XXFIFOSZ_128 0x04u
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#define MUSB_VAL_XXFIFOSZ_256 0x05u
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#define MUSB_VAL_XXFIFOSZ_512 0x06u
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#define MUSB_VAL_XXFIFOSZ_1024 0x07u
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#define MUSB_VAL_XXFIFOSZ_2048 0x08u
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#define MUSB_VAL_XXFIFOSZ_4096 0x09u
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#endif /* !_MUSB_REGS_H_ */
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