2d64210c1d
Written by JP Embedded. Host controller (HCD), mass storage, and hub drivers. Change-Id: I4237cf7aeb4a1c0205a1876593a9cc67ef3d577e
949 lines
27 KiB
C
949 lines
27 KiB
C
/*
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* Implementation of low level MUSB core logic (variant independent)
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*/
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#include <string.h> /* memcpy */
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#include <usbd/hcd_common.h>
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#include <usbd/hcd_interface.h>
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#include <usbd/usbd_common.h>
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#include "musb_core.h"
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#include "musb_regs.h"
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/*===========================================================================*
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* Local prototypes *
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*===========================================================================*/
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static void musb_set_state(musb_core_config *);
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static int musb_check_rxpktrdy(void *, hcd_reg1);
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static void musb_in_stage_cleanup(void *, hcd_reg1);
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static void musb_clear_rxpktrdy(void *, hcd_reg1);
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static void musb_clear_statuspkt(void *);
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static int musb_get_count(void *);
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static void musb_read_fifo(void *, void *, int, hcd_reg1);
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static void musb_write_fifo(void *, void *, int, hcd_reg1);
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/*===========================================================================*
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* *
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* MUSB core implementation *
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* *
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*===========================================================================*/
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/*===========================================================================*
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* musb_set_state *
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*===========================================================================*/
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static void
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musb_set_state(musb_core_config * cfg)
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{
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void * r;
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DEBUG_DUMP;
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r = cfg->regs;
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USB_ASSERT(cfg->ep <= HCD_LAST_EP, "Invalid EP supplied");
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USB_ASSERT(cfg->addr <= HCD_LAST_ADDR, "Invalid address supplied");
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/* Set EP and address to be used in next MUSB command */
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/* Set EP by selecting INDEX */
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HCD_WR1(r, MUSB_REG_INDEX, cfg->ep);
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/* Use device with address 'cfg->addr' */
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HCD_WR1(r, MUSB_REG_FADDR, cfg->addr);
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HCD_WR2(r, MUSB_REG_CONFIG(cfg->ep, MUSB_REG_RXFUNCADDR), cfg->addr);
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HCD_WR2(r, MUSB_REG_CONFIG(cfg->ep, MUSB_REG_TXFUNCADDR), cfg->addr);
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}
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/*===========================================================================*
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* musb_check_rxpktrdy *
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*===========================================================================*/
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static int
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musb_check_rxpktrdy(void * cfg, hcd_reg1 ep_num)
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{
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void * r;
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DEBUG_DUMP;
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r = ((musb_core_config *)cfg)->regs;
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/* Set EP and device address to be used in this command */
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musb_set_state((musb_core_config *)cfg);
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/* Check for RXPKTRDY */
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if (HCD_DEFAULT_EP == ep_num) {
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/* Get control status register for EP 0 */
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if (HCD_RD2(r, MUSB_REG_HOST_CSR0) &
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MUSB_VAL_HOST_CSR0_RXPKTRDY)
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return EXIT_SUCCESS;
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} else {
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/* Get RX status register for any other EP */
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if (HCD_RD2(r, MUSB_REG_HOST_RXCSR) &
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MUSB_VAL_HOST_RXCSR_RXPKTRDY)
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return EXIT_SUCCESS;
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}
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return EXIT_FAILURE;
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}
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/*===========================================================================*
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* musb_in_stage_cleanup *
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*===========================================================================*/
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static void
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musb_in_stage_cleanup(void * cfg, hcd_reg1 ep_num)
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{
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DEBUG_DUMP;
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musb_clear_rxpktrdy(cfg, ep_num);
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/* For control EP 0 also clear STATUSPKT */
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if (HCD_DEFAULT_EP == ep_num)
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musb_clear_statuspkt(cfg);
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}
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/*===========================================================================*
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* musb_clear_rxpktrdy *
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*===========================================================================*/
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static void
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musb_clear_rxpktrdy(void * cfg, hcd_reg1 ep_num)
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{
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void * r;
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hcd_reg2 host_csr;
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DEBUG_DUMP;
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r = ((musb_core_config *)cfg)->regs;
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/* Set EP and device address to be used in this command */
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musb_set_state((musb_core_config *)cfg);
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/* Check for RXPKTRDY */
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if (HCD_DEFAULT_EP == ep_num) {
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/* Get control status register for EP 0 */
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host_csr = HCD_RD2(r, MUSB_REG_HOST_CSR0);
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/* Clear RXPKTRDY to signal receive completion */
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HCD_CLR(host_csr, MUSB_VAL_HOST_CSR0_RXPKTRDY);
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HCD_WR2(r, MUSB_REG_HOST_CSR0, host_csr);
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} else {
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/* Get RX status register for any other EP */
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host_csr = HCD_RD2(r, MUSB_REG_HOST_RXCSR);
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/* Clear RXPKTRDY to signal receive completion */
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HCD_CLR(host_csr, MUSB_VAL_HOST_RXCSR_RXPKTRDY);
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HCD_WR2(r, MUSB_REG_HOST_RXCSR, host_csr);
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}
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}
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/*===========================================================================*
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* musb_clear_statuspkt *
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*===========================================================================*/
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static void
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musb_clear_statuspkt(void * cfg)
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{
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void * r;
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hcd_reg2 host_csr0;
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DEBUG_DUMP;
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r = ((musb_core_config *)cfg)->regs;
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/* Set EP and device address to be used in this command */
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musb_set_state((musb_core_config *)cfg);
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/* Get control status register for EP 0 */
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host_csr0 = HCD_RD2(r, MUSB_REG_HOST_CSR0);
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/* Clear STATUSPKT to signal status packet completion */
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HCD_CLR(host_csr0, MUSB_VAL_HOST_CSR0_STATUSPKT);
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HCD_WR2(r, MUSB_REG_HOST_CSR0, host_csr0);
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}
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/*===========================================================================*
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* musb_get_count *
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*===========================================================================*/
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static int
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musb_get_count(void * cfg)
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{
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void * r;
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DEBUG_DUMP;
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r = ((musb_core_config *)cfg)->regs;
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/* Set EP and device address to be used in this command */
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musb_set_state((musb_core_config *)cfg);
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/* Reserved part returns zero so no need to generalize
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* this return for MUSB_REG_RXCOUNT */
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return (int)(HCD_RD2(r, MUSB_REG_COUNT0));
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}
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/*===========================================================================*
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* musb_read_fifo *
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*===========================================================================*/
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static void
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musb_read_fifo(void * cfg, void * output, int size, hcd_reg1 fifo_num)
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{
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void * r;
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hcd_reg1 * output_b;
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hcd_reg4 * output_w;
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hcd_addr fifo_addr;
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DEBUG_DUMP;
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USB_ASSERT(fifo_num <= HCD_LAST_EP, "Invalid FIFO number");
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r = ((musb_core_config *)cfg)->regs;
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fifo_addr = MUSB_REG_FIFO0 + (fifo_num * MUSB_REG_FIFO_LEN);
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/* TODO: Apparently, FIFO can only be read by:
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* 1. initially using words
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* 2. using bytes for whatever remains
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* Reading bytes first to achieve alignment of remaining data
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* will for some reason disable further word based reading
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* Such reading method, may not be optimal for unaligned data */
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output_w = (hcd_reg4 *)output;
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/* Try and copy aligned words */
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if (0 == ((hcd_addr)output_w % sizeof(hcd_addr))) {
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while (size > (int)(sizeof(*output_w) - 1)) {
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*output_w++ = HCD_RD4(r, fifo_addr);
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size -= sizeof(*output_w);
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}
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}
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output_b = (hcd_reg1 *)output_w;
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/* Then, go with remaining bytes */
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while (size > 0) {
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*output_b++ = HCD_RD1(r, fifo_addr);
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size--;
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}
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}
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/*===========================================================================*
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* musb_write_fifo *
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*===========================================================================*/
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static void
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musb_write_fifo(void * cfg, void * input, int size, hcd_reg1 fifo_num)
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{
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void * r;
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hcd_reg1 * input_b;
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hcd_reg4 * input_w;
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hcd_addr fifo_addr;
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DEBUG_DUMP;
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USB_ASSERT(fifo_num <= HCD_LAST_EP, "Invalid FIFO number");
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r = ((musb_core_config *)cfg)->regs;
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fifo_addr = MUSB_REG_FIFO0 + (fifo_num * MUSB_REG_FIFO_LEN);
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/* TODO: Apparently, FIFO can only be written by:
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* 1. initially using words
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* 2. using bytes for whatever remains
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* Writing bytes first to achieve alignment of remaining data
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* will for some reason disable further word based writing
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* Such writing method, may not be optimal for unaligned data */
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input_w = (hcd_reg4 *)input;
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/* Try and copy aligned words */
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if (0 == ((hcd_addr)input_w % sizeof(hcd_addr))) {
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while (size > (int)(sizeof(*input_w) - 1)) {
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HCD_WR4(r, fifo_addr, *input_w++);
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size -= sizeof(*input_w);
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}
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}
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input_b = (hcd_reg1 *)input_w;
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/* Then, go with remaining bytes */
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while (size > 0) {
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HCD_WR1(r, fifo_addr, *input_b++);
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size--;
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}
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}
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/*===========================================================================*
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* musb_core_start *
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*===========================================================================*/
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void
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musb_core_start(void * cfg)
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{
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void * r;
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hcd_reg1 devctl;
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DEBUG_DUMP;
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r = ((musb_core_config *)cfg)->regs;
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/* Enable all interrupts valid for host */
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HCD_WR1(r, MUSB_REG_INTRUSBE,
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MUSB_VAL_INTRUSBE_SUSPEND |
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MUSB_VAL_INTRUSBE_RESUME |
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MUSB_VAL_INTRUSBE_RESET_BABBLE |
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/* MUSB_VAL_INTRUSBE_SOF | */
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MUSB_VAL_INTRUSBE_CONN |
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MUSB_VAL_INTRUSBE_DISCON |
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MUSB_VAL_INTRUSBE_SESSREQ |
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MUSB_VAL_INTRUSBE_VBUSERR);
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/* Start session */
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devctl = HCD_RD1(r, MUSB_REG_DEVCTL);
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HCD_SET(devctl, MUSB_VAL_DEVCTL_SESSION);
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HCD_WR1(r, MUSB_REG_DEVCTL, devctl);
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}
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/*===========================================================================*
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* musb_core_stop *
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*===========================================================================*/
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void
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musb_core_stop(void * cfg)
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{
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void * r;
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hcd_reg1 devctl;
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DEBUG_DUMP;
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r = ((musb_core_config *)cfg)->regs;
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/* Disable all interrupts */
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HCD_WR1(r, MUSB_REG_INTRUSBE, MUSB_VAL_INTRUSBE_NONE);
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/* Stop session */
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devctl = HCD_RD1(r, MUSB_REG_DEVCTL);
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HCD_CLR(devctl, MUSB_VAL_DEVCTL_SESSION);
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HCD_WR1(r, MUSB_REG_DEVCTL, devctl);
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}
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/*===========================================================================*
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* *
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* HCD interface implementation *
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* *
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*===========================================================================*/
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/*===========================================================================*
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* musb_setup_device *
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*===========================================================================*/
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void
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musb_setup_device(void * cfg, hcd_reg1 ep, hcd_reg1 addr,
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hcd_datatog * tx_tog, hcd_datatog * rx_tog)
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{
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DEBUG_DUMP;
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/* Assign */
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((musb_core_config *)cfg)->ep = ep;
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((musb_core_config *)cfg)->addr = addr;
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((musb_core_config *)cfg)->datatog_tx = tx_tog;
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((musb_core_config *)cfg)->datatog_rx = rx_tog;
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}
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/*===========================================================================*
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* musb_reset_device *
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*===========================================================================*/
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int
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musb_reset_device(void * cfg, hcd_speed * speed)
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{
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void * r;
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musb_core_config * core;
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hcd_reg1 power;
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hcd_reg1 host_type0;
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DEBUG_DUMP;
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core = (musb_core_config *)cfg;
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r = core->regs;
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/* Set initial parameters */
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musb_setup_device(core, HCD_DEFAULT_EP, HCD_DEFAULT_ADDR, NULL, NULL);
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/* Set EP and device address to be used in this command */
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musb_set_state(core);
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/* Write reset bit and high speed negotiation wait for at least
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* 20ms for reset, clear reset bit and wait for device */
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power = HCD_RD1(r, MUSB_REG_POWER);
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HCD_SET(power, MUSB_VAL_POWER_RESET | MUSB_VAL_POWER_HSEN);
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HCD_WR1(r, MUSB_REG_POWER, power);
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/* Sleep 25msec */
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hcd_os_nanosleep(HCD_NANOSLEEP_MSEC(25));
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power = HCD_RD1(r, MUSB_REG_POWER);
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HCD_CLR(power, MUSB_VAL_POWER_RESET);
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HCD_WR1(r, MUSB_REG_POWER, power);
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/* Sleep 25msec */
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hcd_os_nanosleep(HCD_NANOSLEEP_MSEC(25));
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/* High speed check */
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power = HCD_RD1(r, MUSB_REG_POWER);
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if (power & MUSB_VAL_POWER_HSMODE) {
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/* Set high-speed for EP0 */
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host_type0 = HCD_RD1(r, MUSB_REG_HOST_TYPE0);
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HCD_CLR(host_type0, MUSB_VAL_HOST_TYPE0_MASK);
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HCD_SET(host_type0, MUSB_VAL_HOST_TYPE0_HIGH_SPEED);
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HCD_WR1(r, MUSB_REG_HOST_TYPE0, host_type0);
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*speed = HCD_SPEED_HIGH;
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USB_DBG("High speed USB enabled");
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} else {
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/* Only full-speed supported */
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host_type0 = HCD_RD1(r, MUSB_REG_HOST_TYPE0);
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HCD_CLR(host_type0, MUSB_VAL_HOST_TYPE0_MASK);
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HCD_SET(host_type0, MUSB_VAL_HOST_TYPE0_FULL_SPEED);
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HCD_WR1(r, MUSB_REG_HOST_TYPE0, host_type0);
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*speed = HCD_SPEED_FULL;
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USB_DBG("High speed USB disabled");
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}
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return EXIT_SUCCESS;
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}
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/*===========================================================================*
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* musb_setup_stage *
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*===========================================================================*/
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void
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musb_setup_stage(void * cfg, hcd_ctrlrequest * setup)
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{
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void * r;
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char * setup_byte;
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musb_core_config * core;
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hcd_reg2 host_csr0;
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DEBUG_DUMP;
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core = (musb_core_config *)cfg;
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r = core->regs;
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setup_byte = (char*)setup;
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USB_ASSERT(0 == core->ep, "Only EP 0 can handle control transfers");
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/* Set EP and device address to be used in this command */
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musb_set_state(core);
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/* Put USB setup data into EP0 FIFO */
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HCD_WR4(r, MUSB_REG_FIFO0, HCD_8TO32(&setup_byte[0]));
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HCD_WR4(r, MUSB_REG_FIFO0, HCD_8TO32(&setup_byte[sizeof(hcd_reg4)]));
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/* Get control status register for EP 0 */
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host_csr0 = HCD_RD2(r, MUSB_REG_HOST_CSR0);
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/* Send actual packet from FIFO */
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HCD_SET(host_csr0, MUSB_VAL_HOST_CSR0_TXPKTRDY |
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MUSB_VAL_HOST_CSR0_SETUPPKT);
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HCD_WR2(r, MUSB_REG_HOST_CSR0, host_csr0);
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}
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/*===========================================================================*
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* musb_rx_stage *
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*===========================================================================*/
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void
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musb_rx_stage(void * cfg, hcd_datarequest * request)
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{
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musb_core_config * core;
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hcd_reg2 host_rxcsr;
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hcd_reg1 host_rxtype;
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void * r;
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DEBUG_DUMP;
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core = (musb_core_config *)cfg;
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r = core->regs;
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USB_ASSERT(request->max_packet_size <= HCD_MAX_MAXPACKETSIZE,
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"Invalid wMaxPacketSize");
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USB_ASSERT((core->ep <= HCD_LAST_EP) && (core->ep > HCD_DEFAULT_EP),
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"Invalid bulk EP supplied");
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/* Set EP and device address to be used in this command */
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musb_set_state(core);
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/* Evaluate RXTYPE */
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host_rxtype = core->ep;
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switch (request->type) {
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case HCD_TRANSFER_BULK:
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host_rxtype |= MUSB_VAL_HOST_XXTYPE_BULK;
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break;
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case HCD_TRANSFER_INTERRUPT:
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host_rxtype |= MUSB_VAL_HOST_XXTYPE_INTERRUPT;
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break;
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default:
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USB_ASSERT(0, "Unsupported transfer type");
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}
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if (HCD_SPEED_HIGH == request->speed)
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host_rxtype |= MUSB_VAL_HOST_XXTYPE_HIGH_SPEED;
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else
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host_rxtype |= MUSB_VAL_HOST_XXTYPE_FULL_SPEED;
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/* Rewrite HOST_RXTYPE */
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HCD_WR1(r, MUSB_REG_HOST_RXTYPE, host_rxtype);
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/* Rewrite RXMAXP */
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HCD_WR2(r, MUSB_REG_RXMAXP, request->max_packet_size);
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/* Set HOST_RXINTERVAL (which means interval or NAK limit) */
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HCD_WR1(r, MUSB_REG_HOST_RXINTERVAL, request->interval);
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#if 0
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{
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/* Not required by all MUSB implementations, but
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* left here just in case */
|
|
hcd_reg2 intrrxe;
|
|
|
|
/* Enable this interrupt */
|
|
intrrxe = HCD_RD2(r, MUSB_REG_INTRRXE);
|
|
HCD_SET(intrrxe, HCD_BIT(core->ep));
|
|
HCD_WR2(r, MUSB_REG_INTRRXE, intrrxe);
|
|
}
|
|
#endif
|
|
|
|
/* TODO: One reusable FIFO, no double buffering */
|
|
/* TODO: With this, only one device/EP can work at a time. Should this
|
|
* be changed, hcd_device_wait/hcd_device_continue calls must be fixed
|
|
* accordingly to allow handling multiple EP interrupts */
|
|
/* Assign FIFO */
|
|
HCD_WR2(r, MUSB_REG_RXFIFOADDR, MUSB_VAL_XXFIFOADDR_EP0_END);
|
|
HCD_WR1(r, MUSB_REG_RXFIFOSZ, MUSB_VAL_XXFIFOSZ_4096);
|
|
|
|
/* Make controller reconfigure */
|
|
host_rxcsr = HCD_RD2(r, MUSB_REG_HOST_RXCSR);
|
|
HCD_SET(host_rxcsr, MUSB_VAL_HOST_RXCSR_DATATOGWREN); /* Enable first */
|
|
HCD_SET(host_rxcsr, MUSB_VAL_HOST_RXCSR_FLUSHFIFO);
|
|
HCD_WR2(r, MUSB_REG_HOST_RXCSR, host_rxcsr);
|
|
|
|
/* Set data toggle and start receiving */
|
|
host_rxcsr = HCD_RD2(r, MUSB_REG_HOST_RXCSR);
|
|
if (HCD_DATATOG_DATA0 == *(core->datatog_rx))
|
|
HCD_CLR(host_rxcsr, MUSB_VAL_HOST_RXCSR_DATATOG);
|
|
else
|
|
HCD_SET(host_rxcsr, MUSB_VAL_HOST_RXCSR_DATATOG);
|
|
HCD_SET(host_rxcsr, MUSB_VAL_HOST_RXCSR_REQPKT);
|
|
HCD_WR2(r, MUSB_REG_HOST_RXCSR, host_rxcsr);
|
|
}
|
|
|
|
|
|
/*===========================================================================*
|
|
* musb_tx_stage *
|
|
*===========================================================================*/
|
|
void
|
|
musb_tx_stage(void * cfg, hcd_datarequest * request)
|
|
{
|
|
musb_core_config * core;
|
|
hcd_reg2 host_txcsr;
|
|
hcd_reg1 host_txtype;
|
|
void * r;
|
|
|
|
DEBUG_DUMP;
|
|
|
|
core = (musb_core_config *)cfg;
|
|
r = core->regs;
|
|
|
|
USB_ASSERT(request->max_packet_size <= HCD_MAX_MAXPACKETSIZE,
|
|
"Invalid wMaxPacketSize");
|
|
USB_ASSERT((core->ep <= HCD_LAST_EP) && (core->ep > HCD_DEFAULT_EP),
|
|
"Invalid bulk EP supplied");
|
|
|
|
/* Set EP and device address to be used in this command */
|
|
musb_set_state(core);
|
|
|
|
/* Evaluate TXTYPE */
|
|
host_txtype = core->ep;
|
|
|
|
switch (request->type) {
|
|
case HCD_TRANSFER_BULK:
|
|
host_txtype |= MUSB_VAL_HOST_XXTYPE_BULK;
|
|
break;
|
|
case HCD_TRANSFER_INTERRUPT:
|
|
host_txtype |= MUSB_VAL_HOST_XXTYPE_INTERRUPT;
|
|
break;
|
|
default:
|
|
USB_ASSERT(0, "Unsupported transfer type");
|
|
}
|
|
|
|
if (HCD_SPEED_HIGH == request->speed)
|
|
host_txtype |= MUSB_VAL_HOST_XXTYPE_HIGH_SPEED;
|
|
else
|
|
host_txtype |= MUSB_VAL_HOST_XXTYPE_FULL_SPEED;
|
|
|
|
/* Rewrite HOST_TXTYPE */
|
|
HCD_WR1(r, MUSB_REG_HOST_TXTYPE, host_txtype);
|
|
|
|
/* Rewrite TXMAXP */
|
|
HCD_WR2(r, MUSB_REG_TXMAXP, request->max_packet_size);
|
|
|
|
/* Set HOST_TXINTERVAL (which means interval or NAK limit) */
|
|
HCD_WR1(r, MUSB_REG_HOST_TXINTERVAL, request->interval);
|
|
|
|
#if 0
|
|
{
|
|
/* Not required by all MUSB implementations, but
|
|
* left here just in case */
|
|
hcd_reg2 intrtxe;
|
|
|
|
/* Enable this interrupt */
|
|
intrtxe = HCD_RD2(r, MUSB_REG_INTRTXE);
|
|
HCD_SET(intrtxe, HCD_BIT(core->ep));
|
|
HCD_WR2(r, MUSB_REG_INTRTXE, intrtxe);
|
|
}
|
|
#endif
|
|
|
|
/* TODO: One reusable FIFO, no double buffering */
|
|
/* TODO: With this, only one device/EP can work at a time. Should this
|
|
* be changed, hcd_device_wait/hcd_device_continue calls must be fixed
|
|
* accordingly to allow handling multiple EP interrupts */
|
|
/* Assign FIFO */
|
|
HCD_WR2(r, MUSB_REG_TXFIFOADDR, MUSB_VAL_XXFIFOADDR_EP0_END);
|
|
HCD_WR1(r, MUSB_REG_TXFIFOSZ, MUSB_VAL_XXFIFOSZ_4096);
|
|
|
|
/* Make controller reconfigure */
|
|
host_txcsr = HCD_RD2(r, MUSB_REG_HOST_TXCSR);
|
|
HCD_CLR(host_txcsr, MUSB_VAL_HOST_TXCSR_DMAMODE);
|
|
HCD_CLR(host_txcsr, MUSB_VAL_HOST_TXCSR_FRCDATATOG);
|
|
HCD_CLR(host_txcsr, MUSB_VAL_HOST_TXCSR_DMAEN);
|
|
HCD_SET(host_txcsr, MUSB_VAL_HOST_TXCSR_MODE);
|
|
HCD_CLR(host_txcsr, MUSB_VAL_HOST_TXCSR_ISO);
|
|
HCD_CLR(host_txcsr, MUSB_VAL_HOST_TXCSR_AUTOSET);
|
|
HCD_SET(host_txcsr, MUSB_VAL_HOST_TXCSR_DATATOGWREN); /* Enable first */
|
|
/* TODO: May have no effect */
|
|
HCD_SET(host_txcsr, MUSB_VAL_HOST_TXCSR_FLUSHFIFO);
|
|
HCD_WR2(r, MUSB_REG_HOST_TXCSR, host_txcsr);
|
|
|
|
/* Put data in FIFO */
|
|
musb_write_fifo(cfg, request->data, request->data_left, core->ep);
|
|
|
|
/* Set data toggle and start transmitting */
|
|
host_txcsr = HCD_RD2(r, MUSB_REG_HOST_TXCSR);
|
|
if (HCD_DATATOG_DATA0 == *(core->datatog_tx))
|
|
HCD_CLR(host_txcsr, MUSB_VAL_HOST_TXCSR_DATATOG);
|
|
else
|
|
HCD_SET(host_txcsr, MUSB_VAL_HOST_TXCSR_DATATOG);
|
|
HCD_SET(host_txcsr, MUSB_VAL_HOST_TXCSR_TXPKTRDY);
|
|
HCD_WR2(r, MUSB_REG_HOST_TXCSR, host_txcsr);
|
|
}
|
|
|
|
|
|
/*===========================================================================*
|
|
* musb_in_data_stage *
|
|
*===========================================================================*/
|
|
void
|
|
musb_in_data_stage(void * cfg)
|
|
{
|
|
void * r;
|
|
hcd_reg2 host_csr0;
|
|
|
|
DEBUG_DUMP;
|
|
|
|
r = ((musb_core_config *)cfg)->regs;
|
|
|
|
/* Set EP and device address to be used in this command */
|
|
musb_set_state((musb_core_config *)cfg);
|
|
|
|
/* Get control status register for EP 0 */
|
|
host_csr0 = HCD_RD2(r, MUSB_REG_HOST_CSR0);
|
|
|
|
/* Request IN DATA stage */
|
|
HCD_SET(host_csr0, MUSB_VAL_HOST_CSR0_REQPKT);
|
|
HCD_WR2(r, MUSB_REG_HOST_CSR0, host_csr0);
|
|
}
|
|
|
|
|
|
/*===========================================================================*
|
|
* musb_out_data_stage *
|
|
*===========================================================================*/
|
|
void
|
|
musb_out_data_stage(void * cfg)
|
|
{
|
|
DEBUG_DUMP;
|
|
|
|
/* Set EP and device address to be used in this command */
|
|
musb_set_state((musb_core_config *)cfg);
|
|
|
|
/* TODO: Not needed for enumeration but may be needed later, if
|
|
* additional control transfers are implemented */
|
|
USB_ASSERT(0, "Setup packet's 'DATA OUT' stage not implemented");
|
|
}
|
|
|
|
|
|
/*===========================================================================*
|
|
* musb_in_status_stage *
|
|
*===========================================================================*/
|
|
void
|
|
musb_in_status_stage(void * cfg)
|
|
{
|
|
void * r;
|
|
hcd_reg2 host_csr0;
|
|
|
|
DEBUG_DUMP;
|
|
|
|
r = ((musb_core_config *)cfg)->regs;
|
|
|
|
/* Set EP and device address to be used in this command */
|
|
musb_set_state((musb_core_config *)cfg);
|
|
|
|
/* Get control status register for EP 0 */
|
|
host_csr0 = HCD_RD2(r, MUSB_REG_HOST_CSR0);
|
|
|
|
/* Request IN STATUS stage */
|
|
HCD_SET(host_csr0, MUSB_VAL_HOST_CSR0_REQPKT |
|
|
MUSB_VAL_HOST_CSR0_STATUSPKT);
|
|
|
|
HCD_WR2(r, MUSB_REG_HOST_CSR0, host_csr0);
|
|
}
|
|
|
|
|
|
/*===========================================================================*
|
|
* musb_out_status_stage *
|
|
*===========================================================================*/
|
|
void
|
|
musb_out_status_stage(void * cfg)
|
|
{
|
|
void * r;
|
|
hcd_reg2 host_csr0;
|
|
|
|
DEBUG_DUMP;
|
|
|
|
r = ((musb_core_config *)cfg)->regs;
|
|
|
|
/* Set EP and device address to be used in this command */
|
|
musb_set_state((musb_core_config *)cfg);
|
|
|
|
/* Get control status register for EP 0 */
|
|
host_csr0 = HCD_RD2(r, MUSB_REG_HOST_CSR0);
|
|
|
|
/* Request OUT STATUS stage */
|
|
HCD_SET(host_csr0, MUSB_VAL_HOST_CSR0_TXPKTRDY |
|
|
MUSB_VAL_HOST_CSR0_STATUSPKT);
|
|
|
|
HCD_WR2(r, MUSB_REG_HOST_CSR0, host_csr0);
|
|
}
|
|
|
|
|
|
/*===========================================================================*
|
|
* musb_read_data *
|
|
*===========================================================================*/
|
|
int
|
|
musb_read_data(void * cfg, hcd_reg1 * buffer, hcd_reg1 ep_num)
|
|
{
|
|
int count;
|
|
|
|
DEBUG_DUMP;
|
|
|
|
/* Check if anything received at all */
|
|
if (EXIT_SUCCESS != musb_check_rxpktrdy(cfg, ep_num)) {
|
|
USB_MSG("RXPKTRDY not set when receiving");
|
|
return HCD_READ_ERR;
|
|
}
|
|
|
|
/* Number of bytes received at any EP */
|
|
count = musb_get_count(cfg);
|
|
|
|
/* Read from given FIFO */
|
|
if ((NULL != buffer) && (count > 0))
|
|
musb_read_fifo(cfg, buffer, count, ep_num);
|
|
|
|
/* Cleanup after reading */
|
|
musb_in_stage_cleanup(cfg, ep_num);
|
|
|
|
return count;
|
|
}
|
|
|
|
|
|
/*===========================================================================*
|
|
* musb_check_error *
|
|
*===========================================================================*/
|
|
int
|
|
musb_check_error(void * cfg, hcd_transfer xfer, hcd_reg1 ep, hcd_direction dir)
|
|
{
|
|
/* Possible error handling schemes for MUSB */
|
|
typedef enum {
|
|
|
|
MUSB_INVALID_ERROR_CASE,
|
|
MUSB_EP0_ERROR_CASE,
|
|
MUSB_OUT_ERROR_CASE,
|
|
MUSB_IN_ERROR_CASE,
|
|
}
|
|
musb_error_case;
|
|
|
|
musb_core_config * core;
|
|
void * r;
|
|
hcd_reg2 host_csr;
|
|
musb_error_case error_case;
|
|
|
|
DEBUG_DUMP;
|
|
|
|
/* TODO: ISO transfer */
|
|
USB_ASSERT(HCD_TRANSFER_ISOCHRONOUS != xfer,
|
|
"ISO transfer not supported");
|
|
|
|
core = (musb_core_config *)cfg;
|
|
r = core->regs;
|
|
|
|
/* Set EP and device address to be used in this command */
|
|
musb_set_state((musb_core_config *)cfg);
|
|
|
|
/* Resolve which error needs to be checked
|
|
* so we can use proper MUSB registers */
|
|
error_case = MUSB_INVALID_ERROR_CASE;
|
|
|
|
if (HCD_DEFAULT_EP == ep) {
|
|
if (HCD_TRANSFER_CONTROL == xfer)
|
|
/* EP0, control, any direction */
|
|
error_case = MUSB_EP0_ERROR_CASE;
|
|
} else {
|
|
if (HCD_TRANSFER_CONTROL != xfer) {
|
|
if (HCD_DIRECTION_OUT == dir)
|
|
/* EP>0, non-control, out */
|
|
error_case = MUSB_OUT_ERROR_CASE;
|
|
else if (HCD_DIRECTION_IN == dir)
|
|
/* EP>0, non-control, in */
|
|
error_case = MUSB_IN_ERROR_CASE;
|
|
}
|
|
}
|
|
|
|
/* In MUSB, EP0 has it's own registers for error handling and it also
|
|
* seems to be the only way to handle errors for control transfers */
|
|
if (MUSB_EP0_ERROR_CASE == error_case) {
|
|
/* Get control status register */
|
|
host_csr = HCD_RD2(r, MUSB_REG_HOST_CSR0);
|
|
|
|
/* Check for common errors */
|
|
if (host_csr & MUSB_VAL_HOST_CSR0_ERROR) {
|
|
USB_MSG("HOST_CSR0 ERROR: %04X", host_csr);
|
|
HCD_CLR(host_csr, MUSB_VAL_HOST_CSR0_ERROR);
|
|
HCD_WR2(r, MUSB_REG_HOST_CSR0, host_csr);
|
|
return EXIT_FAILURE;
|
|
}
|
|
|
|
if (host_csr & MUSB_VAL_HOST_CSR0_RXSTALL) {
|
|
USB_MSG("HOST_CSR0 STALL: %04X", host_csr);
|
|
HCD_CLR(host_csr, MUSB_VAL_HOST_CSR0_RXSTALL);
|
|
HCD_WR2(r, MUSB_REG_HOST_CSR0, host_csr);
|
|
return EXIT_FAILURE;
|
|
}
|
|
|
|
if (host_csr & MUSB_VAL_HOST_CSR0_NAK_TIMEOUT) {
|
|
USB_MSG("HOST_CSR0 NAK_TIMEOUT: %04X", host_csr);
|
|
HCD_CLR(host_csr, MUSB_VAL_HOST_CSR0_NAK_TIMEOUT);
|
|
HCD_WR2(r, MUSB_REG_HOST_CSR0, host_csr);
|
|
return EXIT_FAILURE;
|
|
}
|
|
|
|
return EXIT_SUCCESS;
|
|
}
|
|
|
|
if (MUSB_OUT_ERROR_CASE == error_case) {
|
|
/* Get TX status register */
|
|
host_csr = HCD_RD2(r, MUSB_REG_HOST_TXCSR);
|
|
|
|
/* Check for completion */
|
|
if (!(host_csr & MUSB_VAL_HOST_TXCSR_TXPKTRDY)) {
|
|
/* ACK received update data toggle */
|
|
*(core->datatog_tx) ^= HCD_DATATOG_DATA1;
|
|
return EXIT_SUCCESS;
|
|
}
|
|
|
|
/* Check for common errors */
|
|
if (host_csr & MUSB_VAL_HOST_TXCSR_ERROR) {
|
|
USB_MSG("HOST_TXCSR ERROR: %04X", host_csr);
|
|
HCD_CLR(host_csr, MUSB_VAL_HOST_TXCSR_ERROR);
|
|
HCD_WR2(r, MUSB_REG_HOST_TXCSR, host_csr);
|
|
return EXIT_FAILURE;
|
|
}
|
|
|
|
if (host_csr & MUSB_VAL_HOST_TXCSR_RXSTALL) {
|
|
USB_MSG("HOST_TXCSR STALL: %04X", host_csr);
|
|
HCD_CLR(host_csr, MUSB_VAL_HOST_TXCSR_RXSTALL);
|
|
HCD_WR2(r, MUSB_REG_HOST_TXCSR, host_csr);
|
|
return EXIT_FAILURE;
|
|
}
|
|
|
|
if (host_csr & MUSB_VAL_HOST_TXCSR_NAK_TIMEOUT) {
|
|
USB_MSG("HOST_TXCSR NAK_TIMEOUT: %04X", host_csr);
|
|
/* Flush FIFO before clearing NAKTIMEOUT
|
|
* to abort transfer */
|
|
HCD_SET(host_csr, MUSB_VAL_HOST_TXCSR_FLUSHFIFO);
|
|
HCD_WR2(r, MUSB_REG_HOST_TXCSR, host_csr);
|
|
host_csr = HCD_RD2(r, MUSB_REG_HOST_TXCSR);
|
|
HCD_CLR(host_csr, MUSB_VAL_HOST_TXCSR_NAK_TIMEOUT);
|
|
HCD_WR2(r, MUSB_REG_HOST_TXCSR, host_csr);
|
|
return EXIT_FAILURE;
|
|
}
|
|
|
|
USB_ASSERT(0, "Invalid state of HOST_TXCSR");
|
|
}
|
|
|
|
if (MUSB_IN_ERROR_CASE == error_case) {
|
|
/* Get RX status register */
|
|
host_csr = HCD_RD2(r, MUSB_REG_HOST_RXCSR);
|
|
|
|
/* Check for completion */
|
|
if (host_csr & MUSB_VAL_HOST_RXCSR_RXPKTRDY) {
|
|
/* ACK received update data toggle */
|
|
*(core->datatog_rx) ^= HCD_DATATOG_DATA1;
|
|
return EXIT_SUCCESS;
|
|
}
|
|
|
|
/* Check for common errors */
|
|
if (host_csr & MUSB_VAL_HOST_RXCSR_ERROR) {
|
|
USB_MSG("HOST_RXCSR ERROR: %04X", host_csr);
|
|
HCD_CLR(host_csr, MUSB_VAL_HOST_RXCSR_ERROR);
|
|
HCD_WR2(r, MUSB_REG_HOST_RXCSR, host_csr);
|
|
return EXIT_FAILURE;
|
|
}
|
|
|
|
if (host_csr & MUSB_VAL_HOST_RXCSR_RXSTALL) {
|
|
USB_MSG("HOST_RXCSR STALL: %04X", host_csr);
|
|
HCD_CLR(host_csr, MUSB_VAL_HOST_RXCSR_RXSTALL);
|
|
HCD_WR2(r, MUSB_REG_HOST_RXCSR, host_csr);
|
|
return EXIT_FAILURE;
|
|
}
|
|
|
|
if (host_csr & MUSB_VAL_HOST_RXCSR_NAKTIMEOUT) {
|
|
USB_MSG("HOST_RXCSR NAK_TIMEOUT: %04X", host_csr);
|
|
/* Clear REQPKT before NAKTIMEOUT to abort transfer */
|
|
HCD_CLR(host_csr, MUSB_VAL_HOST_RXCSR_REQPKT);
|
|
HCD_WR2(r, MUSB_REG_HOST_RXCSR, host_csr);
|
|
host_csr = HCD_RD2(r, MUSB_REG_HOST_RXCSR);
|
|
HCD_CLR(host_csr, MUSB_VAL_HOST_RXCSR_NAKTIMEOUT);
|
|
HCD_WR2(r, MUSB_REG_HOST_RXCSR, host_csr);
|
|
return EXIT_FAILURE;
|
|
}
|
|
|
|
USB_ASSERT(0, "Invalid state of HOST_RXCSR");
|
|
}
|
|
|
|
USB_MSG("Invalid USB transfer error check: 0x%X, 0x%X, 0x%X",
|
|
(int)xfer, (int)ep, (int)dir);
|
|
return EXIT_FAILURE;
|
|
}
|