8ea66915f2
. make read_tsc_64 use the free-running clock, significantly improving scheduling behaviour Change-Id: Idf6a12f6e26be7fe3b3664c278cae846d8b2a442
132 lines
3.3 KiB
C
132 lines
3.3 KiB
C
#include "kernel/kernel.h"
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#include "kernel/clock.h"
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#include <sys/types.h>
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#include <machine/cpu.h>
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#include <io.h>
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#include "arch_proto.h"
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#include "omap_timer.h"
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#include "omap_intr.h"
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static irq_hook_t omap3_timer_hook; /* interrupt handler hook */
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static u64_t high_frc;
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vir_bytes omap3_gptimer10_base;
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int omap3_register_timer_handler(const irq_handler_t handler)
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{
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/* Initialize the CLOCK's interrupt hook. */
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omap3_timer_hook.proc_nr_e = NONE;
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omap3_timer_hook.irq = OMAP3_GPT1_IRQ;
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put_irq_handler(&omap3_timer_hook, OMAP3_GPT1_IRQ, handler);
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return 0;
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}
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void omap3_frclock_init(void)
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{
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u32_t tisr;
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/* Stop timer */
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mmio_clear(OMAP3_GPTIMER10_TCLR, OMAP3_TCLR_ST);
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/* Use functional clock source for GPTIMER10 */
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mmio_set(OMAP3_CM_CLKSEL_CORE, OMAP3_CLKSEL_GPT10);
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/* Scale timer down to 13/8 = 1.625 Mhz to roughly get microsecond ticks */
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/* The scale is computed as 2^(PTV+1). So if PTV == 2, we get 2^3 = 8.
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*/
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mmio_set(OMAP3_GPTIMER10_TCLR, (2 << OMAP3_TCLR_PTV));
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/* Start and auto-reload at 0 */
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mmio_write(OMAP3_GPTIMER10_TLDR, 0x0);
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mmio_write(OMAP3_GPTIMER10_TCRR, 0x0);
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/* Set up overflow interrupt */
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tisr = OMAP3_TISR_MAT_IT_FLAG | OMAP3_TISR_OVF_IT_FLAG |
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OMAP3_TISR_TCAR_IT_FLAG;
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mmio_write(OMAP3_GPTIMER10_TISR, tisr); /* Clear interrupt status */
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mmio_write(OMAP3_GPTIMER10_TIER, OMAP3_TIER_OVF_IT_ENA);
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/* Start timer */
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mmio_set(OMAP3_GPTIMER10_TCLR,
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OMAP3_TCLR_OVF_TRG|OMAP3_TCLR_AR|OMAP3_TCLR_ST|OMAP3_TCLR_PRE);
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}
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void omap3_frclock_stop()
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{
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mmio_clear(OMAP3_GPTIMER10_TCLR, OMAP3_TCLR_ST);
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}
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void omap3_timer_init(unsigned freq)
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{
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u32_t tisr;
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/* Stop timer */
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mmio_clear(OMAP3_GPTIMER1_TCLR, OMAP3_TCLR_ST);
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/* Use 32 KHz clock source for GPTIMER1 */
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mmio_clear(OMAP3_CM_CLKSEL_WKUP, OMAP3_CLKSEL_GPT1);
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/* Use 1-ms tick mode for GPTIMER1 TRM 16.2.4.2.1 */
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mmio_write(OMAP3_GPTIMER1_TPIR, 232000);
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mmio_write(OMAP3_GPTIMER1_TNIR, -768000);
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mmio_write(OMAP3_GPTIMER1_TLDR, 0xffffffe0);
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mmio_write(OMAP3_GPTIMER1_TCRR, 0xffffffe0);
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/* Set up overflow interrupt */
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tisr = OMAP3_TISR_MAT_IT_FLAG | OMAP3_TISR_OVF_IT_FLAG |
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OMAP3_TISR_TCAR_IT_FLAG;
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mmio_write(OMAP3_GPTIMER1_TISR, tisr); /* Clear interrupt status */
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mmio_write(OMAP3_GPTIMER1_TIER, OMAP3_TIER_OVF_IT_ENA);
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omap3_irq_unmask(OMAP3_GPT1_IRQ);
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/* Start timer */
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mmio_set(OMAP3_GPTIMER1_TCLR,
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OMAP3_TCLR_OVF_TRG|OMAP3_TCLR_AR|OMAP3_TCLR_ST);
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}
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void omap3_timer_stop()
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{
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mmio_clear(OMAP3_GPTIMER1_TCLR, OMAP3_TCLR_ST);
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}
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static u32_t read_frc(void)
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{
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u32_t frc = *(u32_t *) ((char *) omap3_gptimer10_base + OMAP3_TCRR);
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return frc;
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}
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static void frc_overflow_check(void)
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{
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static int prev_frc_valid;
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static u32_t prev_frc;
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u32_t cur_frc = read_frc();
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if(prev_frc_valid && prev_frc > cur_frc)
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high_frc++;
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prev_frc = cur_frc;
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prev_frc_valid = 1;
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}
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void omap3_timer_int_handler()
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{
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/* Clear all interrupts */
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u32_t tisr;
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tisr = OMAP3_TISR_MAT_IT_FLAG | OMAP3_TISR_OVF_IT_FLAG |
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OMAP3_TISR_TCAR_IT_FLAG;
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mmio_write(OMAP3_GPTIMER1_TISR, tisr);
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frc_overflow_check();
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}
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/* Use the free running clock as TSC */
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void read_tsc_64(u64_t *t)
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{
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u32_t now;
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frc_overflow_check();
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now = read_frc();
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*t = (u64_t) now + (high_frc << 32);
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}
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