- each CPU has its own runqueues - processes on BSP are put on the runqueues later after a switch to the final stack when cpuid works to avoid special cases - enqueue() and dequeue() use the run queues of the cpu the process is assigned to - pick_proc() uses the local run queues - printing of per-CPU run queues ('2') on serial console
611 lines
13 KiB
C
611 lines
13 KiB
C
/* system dependent functions for use inside the whole kernel. */
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#include "kernel/kernel.h"
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#include <unistd.h>
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#include <ctype.h>
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#include <string.h>
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#include <machine/cmos.h>
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#include <machine/bios.h>
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#include <minix/portio.h>
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#include <minix/cpufeature.h>
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#include <a.out.h>
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#include <assert.h>
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#include <signal.h>
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#include <machine/vm.h>
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#include <sys/sigcontext.h>
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#include "archconst.h"
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#include "arch_proto.h"
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#include "serial.h"
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#include "oxpcie.h"
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#include "kernel/proc.h"
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#include "kernel/debug.h"
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#include "multiboot.h"
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#include "glo.h"
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#ifdef CONFIG_APIC
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#include "apic.h"
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#endif
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#include "acpi.h"
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PRIVATE int osfxsr_feature; /* FXSAVE/FXRSTOR instructions support (SSEx) */
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extern __dead void poweroff_jmp();
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extern void poweroff16();
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extern void poweroff16_end();
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/* set MP and NE flags to handle FPU exceptions in native mode. */
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#define CR0_MP_NE 0x0022
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/* set CR4.OSFXSR[bit 9] if FXSR is supported. */
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#define CR4_OSFXSR (1L<<9)
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/* set OSXMMEXCPT[bit 10] if we provide #XM handler. */
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#define CR4_OSXMMEXCPT (1L<<10)
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PUBLIC void * k_stacks;
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FORWARD _PROTOTYPE( void ser_debug, (int c));
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PUBLIC __dead void arch_monitor(void)
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{
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monitor();
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}
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PRIVATE __dead void arch_bios_poweroff(void)
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{
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u32_t cr0;
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/* Disable paging */
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cr0 = read_cr0();
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cr0 &= ~I386_CR0_PG;
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write_cr0(cr0);
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/* Copy 16-bit poweroff code to below 1M */
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phys_copy(
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FUNC2PHY(&poweroff16),
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BIOS_POWEROFF_ENTRY,
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(u32_t)&poweroff16_end-(u32_t)&poweroff16);
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poweroff_jmp();
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}
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PUBLIC int cpu_has_tsc;
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PUBLIC __dead void arch_shutdown(int how)
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{
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static char mybuffer[sizeof(params_buffer)];
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u16_t magic;
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vm_stop();
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/* Mask all interrupts, including the clock. */
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outb( INT_CTLMASK, ~0);
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if(minix_panicing) {
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/* We're panicing? Then retrieve and decode currently
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* loaded segment selectors.
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*/
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printseg("cs: ", 1, get_cpulocal_var(proc_ptr), read_cs());
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printseg("ds: ", 0, get_cpulocal_var(proc_ptr), read_ds());
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if(read_ds() != read_ss()) {
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printseg("ss: ", 0, NULL, read_ss());
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}
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}
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if (how == RBT_DEFAULT) {
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how = mon_return ? RBT_HALT : RBT_RESET;
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}
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if(how != RBT_RESET) {
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/* return to boot monitor */
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outb( INT_CTLMASK, 0);
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outb( INT2_CTLMASK, 0);
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/* Return to the boot monitor. Set
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* the program if not already done.
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*/
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if (how != RBT_MONITOR)
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arch_set_params("", 1);
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if(minix_panicing) {
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int source, dest;
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const char *lead = "echo \\n*** kernel messages:\\n";
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const int leadlen = strlen(lead);
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strcpy(mybuffer, lead);
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#define DECSOURCE source = (source - 1 + _KMESS_BUF_SIZE) % _KMESS_BUF_SIZE
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dest = sizeof(mybuffer)-1;
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mybuffer[dest--] = '\0';
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source = kmess.km_next;
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DECSOURCE;
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while(dest >= leadlen) {
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const char c = kmess.km_buf[source];
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if(c == '\n') {
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mybuffer[dest--] = 'n';
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mybuffer[dest] = '\\';
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} else if(isprint(c) &&
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c != '\'' && c != '"' &&
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c != '\\' && c != ';') {
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mybuffer[dest] = c;
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} else mybuffer[dest] = ' ';
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DECSOURCE;
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dest--;
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}
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arch_set_params(mybuffer, strlen(mybuffer)+1);
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}
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if (mon_return)
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arch_monitor();
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/* monitor command with no monitor: reset or poweroff
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* depending on the parameters
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*/
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if (how == RBT_MONITOR) {
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mybuffer[0] = '\0';
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arch_get_params(mybuffer, sizeof(mybuffer));
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if (strstr(mybuffer, "boot") ||
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strstr(mybuffer, "menu") ||
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strstr(mybuffer, "reset"))
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how = RBT_RESET;
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else
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how = RBT_HALT;
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}
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}
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switch (how) {
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case RBT_REBOOT:
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case RBT_RESET:
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/* Reset the system by forcing a processor shutdown.
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* First stop the BIOS memory test by setting a soft
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* reset flag.
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*/
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magic = STOP_MEM_CHECK;
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phys_copy(vir2phys(&magic), SOFT_RESET_FLAG_ADDR,
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SOFT_RESET_FLAG_SIZE);
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reset();
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NOT_REACHABLE;
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case RBT_HALT:
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/* Poweroff without boot monitor */
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arch_bios_poweroff();
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NOT_REACHABLE;
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case RBT_PANIC:
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/* Allow user to read panic message */
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for (; ; ) halt_cpu();
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NOT_REACHABLE;
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default:
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/* Not possible! trigger panic */
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assert(how != RBT_MONITOR);
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assert(how != RBT_DEFAULT);
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assert(how < RBT_INVALID);
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panic("unexpected value for how: %d", how);
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NOT_REACHABLE;
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}
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NOT_REACHABLE;
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}
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/* address of a.out headers, set in mpx386.s */
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phys_bytes aout;
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PUBLIC void arch_get_aout_headers(const int i, struct exec *h)
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{
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/* The bootstrap loader created an array of the a.out headers at
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* absolute address 'aout'. Get one element to h.
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*/
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phys_copy(aout + i * A_MINHDR, vir2phys(h), (phys_bytes) A_MINHDR);
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}
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PRIVATE void fpu_init(void)
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{
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unsigned short cw, sw;
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fninit();
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sw = fnstsw();
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fnstcw(&cw);
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if((sw & 0xff) == 0 &&
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(cw & 0x103f) == 0x3f) {
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/* We have some sort of FPU, but don't check exact model.
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* Set CR0_NE and CR0_MP to handle fpu exceptions
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* in native mode. */
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write_cr0(read_cr0() | CR0_MP_NE);
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fpu_presence = 1;
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if(_cpufeature(_CPUF_I386_FXSR)) {
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register struct proc *rp;
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phys_bytes aligned_fp_area;
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u32_t cr4 = read_cr4() | CR4_OSFXSR; /* Enable FXSR. */
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/* OSXMMEXCPT if supported
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* FXSR feature can be available without SSE
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*/
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if(_cpufeature(_CPUF_I386_SSE))
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cr4 |= CR4_OSXMMEXCPT;
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write_cr4(cr4);
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osfxsr_feature = 1;
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for (rp = BEG_PROC_ADDR; rp < END_PROC_ADDR; ++rp) {
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/* FXSR requires 16-byte alignment of memory
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* image, but unfortunately some old tools
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* (probably linker) ignores ".balign 16"
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* applied to our memory image.
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* Thus we have to do manual alignment.
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*/
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aligned_fp_area =
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(phys_bytes) &rp->p_fpu_state.fpu_image;
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if(aligned_fp_area % FPUALIGN) {
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aligned_fp_area += FPUALIGN -
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(aligned_fp_area % FPUALIGN);
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}
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rp->p_fpu_state.fpu_save_area_p =
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(void *) aligned_fp_area;
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}
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} else {
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osfxsr_feature = 0;
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}
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} else {
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/* No FPU presents. */
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fpu_presence = 0;
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osfxsr_feature = 0;
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return;
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}
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}
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PUBLIC void save_fpu(struct proc *pr)
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{
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if(!fpu_presence)
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return;
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/* Save changed FPU context. */
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if(osfxsr_feature) {
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fxsave(pr->p_fpu_state.fpu_save_area_p);
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fninit();
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} else {
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fnsave(pr->p_fpu_state.fpu_save_area_p);
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}
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}
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PUBLIC void restore_fpu(struct proc *pr)
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{
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if(!proc_used_fpu(pr)) {
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fninit();
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pr->p_misc_flags |= MF_FPU_INITIALIZED;
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} else {
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if(osfxsr_feature) {
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fxrstor(pr->p_fpu_state.fpu_save_area_p);
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} else {
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frstor(pr->p_fpu_state.fpu_save_area_p);
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}
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}
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}
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PUBLIC void arch_init(void)
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{
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#ifdef CONFIG_APIC
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/*
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* this is setting kernel segments to cover most of the phys memory. The
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* value is high enough to reach local APIC nad IOAPICs before paging is
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* turned on.
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*/
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prot_set_kern_seg_limit(0xfff00000);
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reload_ds();
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#endif
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idt_init();
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/* FIXME stupid a.out
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* align the stacks in the stack are to the K_STACK_SIZE which is a
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* power of 2
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*/
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k_stacks = (void*) (((vir_bytes)&k_stacks_start + K_STACK_SIZE - 1) &
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~(K_STACK_SIZE - 1));
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#ifndef CONFIG_SMP
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/*
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* use stack 0 and cpu id 0 on a single processor machine, SMP
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* configuration does this in smp_init() for all cpus at once
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*/
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tss_init(0, get_k_stack_top(0));
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#endif
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acpi_init();
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#if defined(CONFIG_APIC) && !defined(CONFIG_SMP)
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if (config_no_apic) {
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BOOT_VERBOSE(printf("APIC disabled, using legacy PIC\n"));
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}
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else if (!apic_single_cpu_init()) {
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BOOT_VERBOSE(printf("APIC not present, using legacy PIC\n"));
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}
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#endif
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fpu_init();
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}
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PUBLIC void ser_putc(char c)
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{
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int i;
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int lsr, thr;
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#if CONFIG_OXPCIE
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oxpcie_putc(c);
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#else
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lsr= COM1_LSR;
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thr= COM1_THR;
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for (i= 0; i<100000; i++)
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{
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if (inb( lsr) & LSR_THRE)
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break;
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}
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outb( thr, c);
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#endif
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}
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/*===========================================================================*
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* do_ser_debug *
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*===========================================================================*/
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PUBLIC void do_ser_debug()
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{
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u8_t c, lsr;
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#if CONFIG_OXPCIE
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{
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int oxin;
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if((oxin = oxpcie_in()) >= 0)
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ser_debug(oxin);
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}
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#endif
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lsr= inb(COM1_LSR);
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if (!(lsr & LSR_DR))
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return;
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c = inb(COM1_RBR);
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ser_debug(c);
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}
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PRIVATE void ser_dump_queue_cpu(unsigned cpu)
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{
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int q;
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struct proc ** rdy_head;
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rdy_head = get_cpu_var(cpu, run_q_head);
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for(q = 0; q < NR_SCHED_QUEUES; q++) {
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struct proc *p;
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if(rdy_head[q]) {
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printf("%2d: ", q);
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for(p = rdy_head[q]; p; p = p->p_nextready) {
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printf("%s / %d ", p->p_name, p->p_endpoint);
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}
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printf("\n");
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}
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}
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}
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PRIVATE void ser_dump_queues(void)
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{
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#ifdef CONFIG_SMP
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unsigned cpu;
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printf("--- run queues ---\n");
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for (cpu = 0; cpu < ncpus; cpu++) {
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printf("CPU %d :\n", cpu);
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ser_dump_queue_cpu(cpu);
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}
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#else
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ser_dump_queue_cpu(0);
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#endif
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}
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PRIVATE void ser_dump_segs(void)
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{
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struct proc *pp;
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for (pp= BEG_PROC_ADDR; pp < END_PROC_ADDR; pp++)
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{
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if (isemptyp(pp))
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continue;
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printf("%d: %s ep %d\n", proc_nr(pp), pp->p_name, pp->p_endpoint);
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printseg("cs: ", 1, pp, pp->p_reg.cs);
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printseg("ds: ", 0, pp, pp->p_reg.ds);
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if(pp->p_reg.ss != pp->p_reg.ds) {
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printseg("ss: ", 0, pp, pp->p_reg.ss);
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}
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}
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}
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PRIVATE void ser_debug(const int c)
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{
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serial_debug_active = 1;
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switch(c)
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{
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case 'Q':
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minix_shutdown(NULL);
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NOT_REACHABLE;
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case '1':
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ser_dump_proc();
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break;
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case '2':
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ser_dump_queues();
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break;
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case '3':
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ser_dump_segs();
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break;
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#if DEBUG_TRACE
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#define TOGGLECASE(ch, flag) \
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case ch: { \
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if(verboseflags & flag) { \
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verboseflags &= ~flag; \
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printf("%s disabled\n", #flag); \
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} else { \
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verboseflags |= flag; \
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printf("%s enabled\n", #flag); \
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} \
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break; \
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}
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TOGGLECASE('8', VF_SCHEDULING)
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TOGGLECASE('9', VF_PICKPROC)
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#endif
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#ifdef CONFIG_APIC
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case 'I':
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dump_apic_irq_state();
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break;
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#endif
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}
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serial_debug_active = 0;
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}
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PUBLIC void ser_dump_proc()
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{
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struct proc *pp;
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for (pp= BEG_PROC_ADDR; pp < END_PROC_ADDR; pp++)
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{
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if (isemptyp(pp))
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continue;
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print_proc_recursive(pp);
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}
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}
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#if SPROFILE
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PUBLIC int arch_init_profile_clock(const u32_t freq)
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{
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int r;
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/* Set CMOS timer frequency. */
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outb(RTC_INDEX, RTC_REG_A);
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outb(RTC_IO, RTC_A_DV_OK | freq);
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/* Enable CMOS timer interrupts. */
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outb(RTC_INDEX, RTC_REG_B);
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r = inb(RTC_IO);
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outb(RTC_INDEX, RTC_REG_B);
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outb(RTC_IO, r | RTC_B_PIE);
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/* Mandatory read of CMOS register to enable timer interrupts. */
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outb(RTC_INDEX, RTC_REG_C);
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inb(RTC_IO);
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return CMOS_CLOCK_IRQ;
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}
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PUBLIC void arch_stop_profile_clock(void)
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{
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int r;
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/* Disable CMOS timer interrupts. */
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outb(RTC_INDEX, RTC_REG_B);
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r = inb(RTC_IO);
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outb(RTC_INDEX, RTC_REG_B);
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outb(RTC_IO, r & ~RTC_B_PIE);
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}
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PUBLIC void arch_ack_profile_clock(void)
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{
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/* Mandatory read of CMOS register to re-enable timer interrupts. */
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outb(RTC_INDEX, RTC_REG_C);
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inb(RTC_IO);
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}
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#endif
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#define COLOR_BASE 0xB8000L
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PRIVATE void cons_setc(const int pos, const int c)
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{
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char ch;
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ch= c;
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phys_copy(vir2phys((vir_bytes)&ch), COLOR_BASE+(20*80+pos)*2, 1);
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}
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PRIVATE void cons_seth(int pos, int n)
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{
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n &= 0xf;
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if (n < 10)
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cons_setc(pos, '0'+n);
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else
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cons_setc(pos, 'A'+(n-10));
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}
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/* Saved by mpx386.s into these variables. */
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u32_t params_size, params_offset, mon_ds;
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PUBLIC int arch_get_params(char *params, int maxsize)
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{
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phys_copy(seg2phys(mon_ds) + params_offset, vir2phys(params),
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MIN(maxsize, params_size));
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params[maxsize-1] = '\0';
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return OK;
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}
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PUBLIC int arch_set_params(char *params, int size)
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{
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if(size > params_size)
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return E2BIG;
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phys_copy(vir2phys(params), seg2phys(mon_ds) + params_offset, size);
|
|
return OK;
|
|
}
|
|
|
|
PUBLIC void arch_do_syscall(struct proc *proc)
|
|
{
|
|
/* do_ipc assumes that it's running because of the current process */
|
|
assert(proc == get_cpulocal_var(proc_ptr));
|
|
/* Make the system call, for real this time. */
|
|
proc->p_reg.retreg =
|
|
do_ipc(proc->p_reg.cx, proc->p_reg.retreg, proc->p_reg.bx);
|
|
}
|
|
|
|
PUBLIC struct proc * arch_finish_switch_to_user(void)
|
|
{
|
|
char * stk;
|
|
struct proc * p;
|
|
|
|
#ifdef CONFIG_SMP
|
|
stk = (char *)tss[cpuid].sp0;
|
|
#else
|
|
stk = (char *)tss[0].sp0;
|
|
#endif
|
|
/* set pointer to the process to run on the stack */
|
|
p = get_cpulocal_var(proc_ptr);
|
|
*((reg_t *)stk) = (reg_t) p;
|
|
return p;
|
|
}
|
|
|
|
PUBLIC void fpu_sigcontext(struct proc *pr, struct sigframe *fr, struct sigcontext *sc)
|
|
{
|
|
int fp_error;
|
|
|
|
if (osfxsr_feature) {
|
|
fp_error = sc->sc_fpu_state.xfp_regs.fp_status &
|
|
~sc->sc_fpu_state.xfp_regs.fp_control;
|
|
} else {
|
|
fp_error = sc->sc_fpu_state.fpu_regs.fp_status &
|
|
~sc->sc_fpu_state.fpu_regs.fp_control;
|
|
}
|
|
|
|
if (fp_error & 0x001) { /* Invalid op */
|
|
/*
|
|
* swd & 0x240 == 0x040: Stack Underflow
|
|
* swd & 0x240 == 0x240: Stack Overflow
|
|
* User must clear the SF bit (0x40) if set
|
|
*/
|
|
fr->sf_code = FPE_FLTINV;
|
|
} else if (fp_error & 0x004) {
|
|
fr->sf_code = FPE_FLTDIV; /* Divide by Zero */
|
|
} else if (fp_error & 0x008) {
|
|
fr->sf_code = FPE_FLTOVF; /* Overflow */
|
|
} else if (fp_error & 0x012) {
|
|
fr->sf_code = FPE_FLTUND; /* Denormal, Underflow */
|
|
} else if (fp_error & 0x020) {
|
|
fr->sf_code = FPE_FLTRES; /* Precision */
|
|
} else {
|
|
fr->sf_code = 0; /* XXX - probably should be used for FPE_INTOVF or
|
|
* FPE_INTDIV */
|
|
}
|
|
}
|