179 lines
3.5 KiB
C
179 lines
3.5 KiB
C
/* system dependent functions for use inside the whole kernel. */
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#include "../../kernel.h"
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#include <unistd.h>
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#include <ibm/cmos.h>
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#include <ibm/bios.h>
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#include <minix/portio.h>
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#include "proto.h"
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FORWARD _PROTOTYPE( void do_ser_debug, (void));
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FORWARD _PROTOTYPE( void ser_debug, (int c));
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PUBLIC void arch_shutdown(int how)
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{
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/* Mask all interrupts, including the clock. */
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outb( INT_CTLMASK, ~0);
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if(how != RBT_RESET) {
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/* return to boot monitor */
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outb( INT_CTLMASK, 0);
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outb( INT2_CTLMASK, 0);
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/* Return to the boot monitor. Set
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* the program if not already done.
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*/
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if (how != RBT_MONITOR)
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phys_copy(vir2phys(""), kinfo.params_base, 1);
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level0(monitor);
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} else {
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/* Reset the system by forcing a processor shutdown. First stop
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* the BIOS memory test by setting a soft reset flag.
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*/
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u16_t magic = STOP_MEM_CHECK;
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phys_copy(vir2phys(&magic), SOFT_RESET_FLAG_ADDR,
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SOFT_RESET_FLAG_SIZE);
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level0(reset);
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}
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}
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PUBLIC void system_init(void)
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{
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prot_init();
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}
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#define COM1_BASE 0x3F8
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#define COM1_THR (COM1_BASE + 0)
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#define LSR_THRE 0x20
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#define COM1_LSR (COM1_BASE + 5)
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#define REG_RBR 0
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#define REG_LSR 5
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#define LSR_DR 0x1
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#define COM1_RBR (COM1_BASE + REG_RBR)
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#define COM1_LSR (COM1_BASE + REG_LSR)
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PUBLIC void ser_putc(char c)
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{
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int i;
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int lsr, thr;
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lsr= COM1_LSR;
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thr= COM1_THR;
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for (i= 0; i<100000; i++)
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{
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if (inb( lsr) & LSR_THRE)
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break;
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}
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outb( thr, c);
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}
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/*===========================================================================*
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* do_ser_debug *
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*===========================================================================*/
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PRIVATE void do_ser_debug()
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{
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u8_t c, lsr;
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lsr= inb(COM1_LSR);
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if (!(lsr & LSR_DR))
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return;
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c = inb(COM1_RBR);
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ser_debug(c);
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}
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PRIVATE void ser_debug(int c)
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{
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do_serial_debug++;
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kprintf("ser_debug: %d\n", c);
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switch(c)
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{
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case '1':
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ser_dump_proc();
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break;
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}
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do_serial_debug--;
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}
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PUBLIC void ser_dump_proc()
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{
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struct proc *pp;
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for (pp= BEG_PROC_ADDR; pp < END_PROC_ADDR; pp++)
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{
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if (pp->p_rts_flags & SLOT_FREE)
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continue;
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kprintf(
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"%d: 0x%02x %s e %d src %d dst %d prio %d/%d time %d/%d EIP 0x%x\n",
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proc_nr(pp),
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pp->p_rts_flags, pp->p_name,
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pp->p_endpoint, pp->p_getfrom_e, pp->p_sendto_e,
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pp->p_priority, pp->p_max_priority,
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pp->p_user_time, pp->p_sys_time,
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pp->p_reg.pc);
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}
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}
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#if SPROFILE
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PUBLIC int arch_init_profile_clock(u32_t freq)
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{
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int r;
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/* Set CMOS timer frequency. */
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outb(RTC_INDEX, RTC_REG_A);
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outb(RTC_IO, RTC_A_DV_OK | freq);
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/* Enable CMOS timer interrupts. */
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outb(RTC_INDEX, RTC_REG_B);
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r = inb(RTC_IO);
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outb(RTC_INDEX, RTC_REG_B);
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outb(RTC_IO, r | RTC_B_PIE);
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/* Mandatory read of CMOS register to enable timer interrupts. */
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outb(RTC_INDEX, RTC_REG_C);
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inb(RTC_IO);
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return CMOS_CLOCK_IRQ;
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}
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PUBLIC void arch_stop_profile_clock(void)
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{
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int r;
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/* Disable CMOS timer interrupts. */
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outb(RTC_INDEX, RTC_REG_B);
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r = inb(RTC_IO);
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outb(RTC_INDEX, RTC_REG_B);
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outb(RTC_IO, r & ~RTC_B_PIE);
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}
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PUBLIC void arch_ack_profile_clock(void)
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{
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/* Mandatory read of CMOS register to re-enable timer interrupts. */
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outb(RTC_INDEX, RTC_REG_C);
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inb(RTC_IO);
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}
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#endif
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#define COLOR_BASE 0xB8000L
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PUBLIC void cons_setc(int pos, int c)
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{
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char ch;
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ch= c;
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phys_copy(vir2phys((vir_bytes)&ch), COLOR_BASE+(20*80+pos)*2, 1);
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}
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PUBLIC void cons_seth(int pos, int n)
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{
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n &= 0xf;
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if (n < 10)
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cons_setc(pos, '0'+n);
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else
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cons_setc(pos, 'A'+(n-10));
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}
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