491 lines
12 KiB
C
491 lines
12 KiB
C
/*
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* APIC handling routines. APIC is a requirement for SMP
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*/
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#include "../../kernel.h"
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#include <unistd.h>
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#include <ibm/cmos.h>
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#include <ibm/bios.h>
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#include <minix/portio.h>
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#include <minix/syslib.h>
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#include "../../proc.h"
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#include "../..//glo.h"
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#include "proto.h"
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#include <minix/u64.h>
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#include "apic.h"
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#include "apic_asm.h"
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#include "../../clock.h"
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#include "glo.h"
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#ifdef CONFIG_WATCHDOG
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#include "../../watchdog.h"
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#endif
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#define IA32_APIC_BASE 0x1b
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#define IA32_APIC_BASE_ENABLE_BIT 11
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/* currently only 2 interrupt priority levels are used */
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#define SPL0 0x0
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#define SPLHI 0xF
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/*
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* to make APIC work if SMP is not configured, we need to set the maximal number
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* of CPUS to 1, cpuid to return 0 and the current cpu is always BSP
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*/
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#define CONFIG_MAX_CPUS 1
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#define cpu_is_bsp(x) 1
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#define lapic_write_icr1(val) lapic_write(LAPIC_ICR1, val)
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#define lapic_write_icr2(val) lapic_write(LAPIC_ICR2, val)
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#define lapic_read_icr1(x) lapic_read(LAPIC_ICR1)
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#define lapic_read_icr2(x) lapic_read(LAPIC_ICR2)
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#define VERBOSE_APIC(x) x
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PUBLIC int reboot_type;
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PUBLIC int ioapic_enabled;
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PUBLIC u32_t ioapic_id_mask[8], lapic_id_mask[8];
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PUBLIC u32_t lapic_addr_vaddr;
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PUBLIC u32_t lapic_addr;
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PUBLIC u32_t lapic_eoi_addr;
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PUBLIC u32_t lapic_taskpri_addr;
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PUBLIC int bsp_lapic_id;
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PRIVATE volatile int probe_ticks;
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PRIVATE u64_t tsc0, tsc1;
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PRIVATE u32_t lapic_tctr0, lapic_tctr1;
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u8_t apicid2cpuid[MAX_NR_APICIDS+1];
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unsigned apic_imcrp;
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unsigned nioapics;
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unsigned nbuses;
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unsigned nintrs;
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unsigned nlints;
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/*
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* FIXME this should be a cpulocal variable but there are some problems with
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* arch specific cpulocals. As this variable is write-once-read-only it is ok to
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* have at as an array until we resolve the cpulocals properly
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*/
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PRIVATE u32_t lapic_bus_freq[CONFIG_MAX_CPUS];
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/* the probe period will be roughly 100ms */
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#define PROBE_TICKS (system_hz / 10)
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PRIVATE u32_t pci_config_intr_data;
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PRIVATE u32_t ioapic_extint_assigned = 0;
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PRIVATE int lapic_extint_assigned = 0;
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PRIVATE int calib_clk_handler(irq_hook_t * hook)
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{
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u32_t tcrt;
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u64_t tsc;
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probe_ticks++;
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read_tsc_64(&tsc);
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tcrt = lapic_read(LAPIC_TIMER_CCR);
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if (probe_ticks == 1) {
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lapic_tctr0 = tcrt;
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tsc0 = tsc;
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}
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else if (probe_ticks == PROBE_TICKS) {
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lapic_tctr1 = tcrt;
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tsc1 = tsc;
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}
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return 1;
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}
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PUBLIC void apic_calibrate_clocks(void)
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{
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u32_t lvtt, val, lapic_delta;
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u64_t tsc_delta;
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u32_t cpu_freq;
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irq_hook_t calib_clk;
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BOOT_VERBOSE(kprintf("Calibrating clock\n"));
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/*
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* Set Initial count register to the highest value so it does not
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* underflow during the testing period
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* */
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val = 0xffffffff;
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lapic_write (LAPIC_TIMER_ICR, val);
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/* Set Current count register */
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val = 0;
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lapic_write (LAPIC_TIMER_CCR, val);
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lvtt = lapic_read(LAPIC_TIMER_DCR) & ~0x0b;
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/* Set Divide configuration register to 1 */
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lvtt = APIC_TDCR_1;
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lapic_write(LAPIC_TIMER_DCR, lvtt);
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/*
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* mask the APIC timer interrupt in the LVT Timer Register so that we
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* don't get an interrupt upon underflow which we don't know how to
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* handle right know. If underflow happens, the system will not continue
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* as something is wrong with the clock IRQ 0 and we cannot calibrate
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* the clock which mean that we cannot run processes
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*/
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lvtt = lapic_read (LAPIC_LVTTR);
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lvtt |= APIC_LVTT_MASK;
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lapic_write (LAPIC_LVTTR, lvtt);
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/* set the probe, we use the legacy timer, IRQ 0 */
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put_irq_handler(&calib_clk, CLOCK_IRQ, calib_clk_handler);
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/* set the PIC timer to get some time */
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intr_enable();
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init_8253A_timer(system_hz);
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/* loop for some time to get a sample */
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while(probe_ticks < PROBE_TICKS);
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intr_disable();
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stop_8253A_timer();
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/* remove the probe */
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rm_irq_handler(&calib_clk);
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lapic_delta = lapic_tctr0 - lapic_tctr1;
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tsc_delta = sub64(tsc1, tsc0);
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lapic_bus_freq[cpuid] = system_hz * lapic_delta / (PROBE_TICKS - 1);
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BOOT_VERBOSE(kprintf("APIC bus freq %lu MHz\n",
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lapic_bus_freq[cpuid] / 1000000));
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cpu_freq = div64u(tsc_delta, PROBE_TICKS - 1) * system_hz;
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BOOT_VERBOSE(kprintf("CPU %d freq %lu MHz\n", cpuid,
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cpu_freq / 1000000));
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cpu_set_freq(cpuid, cpu_freq);
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}
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PRIVATE void lapic_set_timer_one_shot(u32_t value)
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{
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/* sleep in micro seconds */
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u32_t lvtt;
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u32_t ticks_per_us;
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u8_t cpu = cpuid;
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ticks_per_us = lapic_bus_freq[cpu] / 1000000;
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/* calculate divisor and count from value */
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lvtt = APIC_TDCR_1;
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lapic_write(LAPIC_TIMER_DCR, lvtt);
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/* configure timer as one-shot */
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lvtt = APIC_TIMER_INT_VECTOR;
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lapic_write(LAPIC_LVTTR, lvtt);
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lapic_write(LAPIC_TIMER_ICR, value * ticks_per_us);
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}
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PUBLIC void lapic_set_timer_periodic(unsigned freq)
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{
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/* sleep in micro seconds */
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u32_t lvtt;
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u32_t lapic_ticks_per_clock_tick;
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u8_t cpu = cpuid;
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lapic_ticks_per_clock_tick = lapic_bus_freq[cpu] / freq;
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lvtt = APIC_TDCR_1;
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lapic_write(LAPIC_TIMER_DCR, lvtt);
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/* configure timer as periodic */
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lvtt = APIC_LVTT_TM | APIC_TIMER_INT_VECTOR;
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lapic_write(LAPIC_LVTTR, lvtt);
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lapic_write(LAPIC_TIMER_ICR, lapic_ticks_per_clock_tick);
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}
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PUBLIC void lapic_stop_timer(void)
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{
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u32_t lvtt;
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lvtt = lapic_read(LAPIC_LVTTR);
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lapic_write(LAPIC_LVTTR, lvtt | APIC_LVTT_MASK);
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}
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PUBLIC void lapic_microsec_sleep(unsigned count)
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{
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lapic_set_timer_one_shot(count);
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while (lapic_read (LAPIC_TIMER_CCR));
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}
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PUBLIC u32_t lapic_errstatus (void)
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{
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lapic_write(LAPIC_ESR, 0);
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return lapic_read(LAPIC_ESR);
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}
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PUBLIC void lapic_disable(void)
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{
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/* Disable current APIC and close interrupts from PIC */
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u32_t val;
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if (!lapic_addr)
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return;
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{
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/* leave it enabled if imcr is not set */
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val = lapic_read(LAPIC_LINT0);
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val &= ~(APIC_ICR_DM_MASK|APIC_ICR_INT_MASK);
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val |= APIC_ICR_DM_EXTINT; /* ExtINT at LINT0 */
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lapic_write (LAPIC_LINT0, val);
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return;
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}
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val = lapic_read(LAPIC_LINT0) & 0xFFFE58FF;
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val |= APIC_ICR_INT_MASK;
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lapic_write (LAPIC_LINT0, val);
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val = lapic_read(LAPIC_LINT1) & 0xFFFE58FF;
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val |= APIC_ICR_INT_MASK;
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lapic_write (LAPIC_LINT1, val);
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val = lapic_read(LAPIC_SIVR) & 0xFFFFFF00;
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val &= ~APIC_ENABLE;
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lapic_write(LAPIC_SIVR, val);
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}
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PRIVATE void lapic_enable_no_lints(void)
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{
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u32_t val;
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val = lapic_read(LAPIC_LINT0);
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lapic_extint_assigned = (val & APIC_ICR_DM_MASK) == APIC_ICR_DM_EXTINT;
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val &= ~(APIC_ICR_DM_MASK|APIC_ICR_INT_MASK);
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if (!ioapic_enabled && cpu_is_bsp(cpuid))
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val |= (APIC_ICR_DM_EXTINT); /* ExtINT at LINT0 */
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else
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val |= (APIC_ICR_DM_EXTINT|APIC_ICR_INT_MASK); /* Masked ExtINT at LINT0 */
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lapic_write (LAPIC_LINT0, val);
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val = lapic_read(LAPIC_LINT1);
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val &= ~(APIC_ICR_DM_MASK|APIC_ICR_INT_MASK);
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if (!ioapic_enabled && cpu_is_bsp(cpuid))
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val |= APIC_ICR_DM_NMI;
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else
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val |= (APIC_ICR_DM_NMI | APIC_ICR_INT_MASK); /* NMI at LINT1 */
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lapic_write (LAPIC_LINT1, val);
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}
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PRIVATE int lapic_enable_in_msr(void)
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{
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u64_t msr;
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u32_t addr;
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ia32_msr_read(IA32_APIC_BASE, &msr.hi, &msr.lo);
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/*
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* FIXME if the location is different (unlikely) then the one we expect,
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* update it
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*/
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addr = (msr.lo >> 12) | ((msr.hi & 0xf) << 20);
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if (phys2vir(addr) != (lapic_addr >> 12)) {
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if (msr.hi & 0xf) {
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kprintf("ERROR : APIC address needs more then 32 bits\n");
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return 0;
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}
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lapic_addr = phys2vir(msr.lo & ~((1 << 12) - 1));
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}
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msr.lo |= (1 << IA32_APIC_BASE_ENABLE_BIT);
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ia32_msr_write(IA32_APIC_BASE, msr.hi, msr.lo);
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return 1;
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}
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PUBLIC int lapic_enable(void)
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{
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u32_t val, nlvt;
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unsigned cpu = cpuid;
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if (!lapic_addr)
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return 0;
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cpu_has_tsc = _cpufeature(_CPUF_I386_TSC);
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if (!cpu_has_tsc) {
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kprintf("CPU lacks timestamp counter, "
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"cannot calibrate LAPIC timer\n");
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return 0;
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}
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if (!lapic_enable_in_msr())
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return 0;
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lapic_eoi_addr = LAPIC_EOI;
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/* clear error state register. */
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val = lapic_errstatus ();
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/* Enable Local APIC and set the spurious vector to 0xff. */
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val = lapic_read(LAPIC_SIVR) & 0xFFFFFF00;
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val |= APIC_ENABLE | APIC_SPURIOUS_INT_VECTOR;
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val &= ~APIC_FOCUS_DISABLED;
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lapic_write(LAPIC_SIVR, val);
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lapic_read(LAPIC_SIVR);
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*((u32_t *)lapic_eoi_addr) = 0;
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cpu = cpuid;
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/* Program Logical Destination Register. */
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val = lapic_read(LAPIC_LDR) & ~0xFF000000;
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val |= (cpu & 0xFF) << 24;
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lapic_write(LAPIC_LDR, val);
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/* Program Destination Format Register for Flat mode. */
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val = lapic_read(LAPIC_DFR) | 0xF0000000;
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lapic_write (LAPIC_DFR, val);
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if (nlints == 0) {
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lapic_enable_no_lints();
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}
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val = lapic_read (LAPIC_LVTER) & 0xFFFFFF00;
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lapic_write (LAPIC_LVTER, val);
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nlvt = (lapic_read(LAPIC_VERSION)>>16) & 0xFF;
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if(nlvt >= 4) {
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val = lapic_read(LAPIC_LVTTMR);
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lapic_write(LAPIC_LVTTMR, val | APIC_ICR_INT_MASK);
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}
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if(nlvt >= 5) {
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val = lapic_read(LAPIC_LVTPCR);
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lapic_write(LAPIC_LVTPCR, val | APIC_ICR_INT_MASK);
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}
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/* setup TPR to allow all interrupts. */
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val = lapic_read (LAPIC_TPR);
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/* accept all interrupts */
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lapic_write (LAPIC_TPR, val & ~0xFF);
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lapic_read (LAPIC_SIVR);
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*((u32_t *)lapic_eoi_addr) = 0;
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apic_calibrate_clocks();
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BOOT_VERBOSE(kprintf("APIC timer calibrated\n"));
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return 1;
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}
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PRIVATE void apic_spurios_intr(void)
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{
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kprintf("WARNING spurious interrupt\n");
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for(;;);
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}
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PRIVATE struct gate_table_s gate_table_ioapic[] = {
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{ apic_hwint00, VECTOR( 0), INTR_PRIVILEGE },
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{ apic_hwint01, VECTOR( 1), INTR_PRIVILEGE },
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{ apic_hwint02, VECTOR( 2), INTR_PRIVILEGE },
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{ apic_hwint03, VECTOR( 3), INTR_PRIVILEGE },
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{ apic_hwint04, VECTOR( 4), INTR_PRIVILEGE },
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{ apic_hwint05, VECTOR( 5), INTR_PRIVILEGE },
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{ apic_hwint06, VECTOR( 6), INTR_PRIVILEGE },
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{ apic_hwint07, VECTOR( 7), INTR_PRIVILEGE },
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{ apic_hwint08, VECTOR( 8), INTR_PRIVILEGE },
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{ apic_hwint09, VECTOR( 9), INTR_PRIVILEGE },
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{ apic_hwint10, VECTOR(10), INTR_PRIVILEGE },
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{ apic_hwint11, VECTOR(11), INTR_PRIVILEGE },
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{ apic_hwint12, VECTOR(12), INTR_PRIVILEGE },
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{ apic_hwint13, VECTOR(13), INTR_PRIVILEGE },
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{ apic_hwint14, VECTOR(14), INTR_PRIVILEGE },
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{ apic_hwint15, VECTOR(15), INTR_PRIVILEGE },
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{ apic_spurios_intr, APIC_SPURIOUS_INT_VECTOR, INTR_PRIVILEGE },
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{ NULL, 0, 0}
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};
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PRIVATE struct gate_table_s gate_table_common[] = {
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{ syscall_entry, SYS386_VECTOR, USER_PRIVILEGE },
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{ level0_call, LEVEL0_VECTOR, TASK_PRIVILEGE },
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{ NULL, 0, 0}
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};
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#ifdef CONFIG_APIC_DEBUG
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PRIVATE void lapic_set_dummy_handlers(void)
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{
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char * handler;
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int vect = 32;
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handler = &lapic_intr_dummy_handles_start;
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handler += vect * LAPIC_INTR_DUMMY_HANDLER_SIZE;
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for(; handler < &lapic_intr_dummy_handles_end;
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handler += LAPIC_INTR_DUMMY_HANDLER_SIZE) {
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int_gate(vect++, (vir_bytes) handler,
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PRESENT | INT_GATE_TYPE |
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(INTR_PRIVILEGE << DPL_SHIFT));
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}
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}
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#endif
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/* Build descriptors for interrupt gates in IDT. */
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PUBLIC void apic_idt_init(int reset)
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{
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/* Set up idt tables for smp mode.
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*/
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vir_bytes local_timer_intr_handler;
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if (reset) {
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idt_copy_vectors(gate_table_pic);
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idt_copy_vectors(gate_table_common);
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return;
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}
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#ifdef CONFIG_APIC_DEBUG
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if (cpu_is_bsp(cpuid))
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kprintf("APIC debugging is enabled\n");
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lapic_set_dummy_handlers();
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#endif
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/* Build descriptors for interrupt gates in IDT. */
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if (ioapic_enabled)
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idt_copy_vectors(gate_table_ioapic);
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else
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idt_copy_vectors(gate_table_pic);
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idt_copy_vectors(gate_table_common);
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/* configure the timer interupt handler */
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if (cpu_is_bsp(cpuid)) {
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local_timer_intr_handler = (vir_bytes) lapic_bsp_timer_int_handler;
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BOOT_VERBOSE(kprintf("Initiating BSP timer handler\n"));
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} else {
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local_timer_intr_handler = (vir_bytes) lapic_ap_timer_int_handler;
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BOOT_VERBOSE(kprintf("Initiating AP timer handler\n"));
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}
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/* register the timer interrupt handler for this CPU */
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int_gate(APIC_TIMER_INT_VECTOR, (vir_bytes) local_timer_intr_handler,
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PRESENT | INT_GATE_TYPE | (INTR_PRIVILEGE << DPL_SHIFT));
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}
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PUBLIC int apic_single_cpu_init(void)
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{
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if (!cpu_feature_apic_on_chip())
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return 0;
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lapic_addr = phys2vir(LOCAL_APIC_DEF_ADDR);
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|
ioapic_enabled = 0;
|
|
|
|
if (!lapic_enable()) {
|
|
lapic_addr = 0x0;
|
|
return 0;
|
|
}
|
|
|
|
apic_idt_init(0); /* Not a reset ! */
|
|
idt_reload();
|
|
return 1;
|
|
}
|