0d2d8c6db2
sb16: port of isa sb16 driver to user-space. Port by Peter Boonstoppel. es1371: By Laurens Bronwasser.
139 lines
6.1 KiB
C
Executable file
139 lines
6.1 KiB
C
Executable file
#ifndef ES1371_H
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#define ES1371_H
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#include <sys/types.h>
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#include "../../drivers.h"
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#include "../../libpci/pci.h"
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#include <sys/ioc_sound.h>
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#define DAC1_CHAN 0
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#define ADC1_CHAN 1
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#define MIXER 2
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#define DAC2_CHAN 3
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/* set your vendor and device ID's here */
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#define VENDOR_ID 0x1274
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#define DEVICE_ID 0x1371
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/* Concert97 direct register offset defines */
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#define CONC_bDEVCTL_OFF 0x00 /* Device control/enable */
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#define CONC_bMISCCTL_OFF 0x01 /* Miscellaneous control */
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#define CONC_bGPIO_OFF 0x02 /* General purpose I/O control */
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#define CONC_bJOYCTL_OFF 0x03 /* Joystick control (decode) */
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#define CONC_bINTSTAT_OFF 0x04 /* Device interrupt status */
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#define CONC_bCODECSTAT_OFF 0x05 /* CODEC interface status */
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#define CONC_bINTSUMM_OFF 0x07 /* Interrupt summary status */
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#define CONC_b4SPKR_OFF 0x07 /* Also 4 speaker config reg */
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#define CONC_bSPDIF_ROUTE_OFF 0x07 /* Also S/PDIF route control reg */
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#define CONC_bUARTDATA_OFF 0x08 /* UART data R/W - read clears RX int */
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#define CONC_bUARTCSTAT_OFF 0x09 /* UART control and status */
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#define CONC_bUARTTEST_OFF 0x0a /* UART test control reg */
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#define CONC_bMEMPAGE_OFF 0x0c /* Memory page select */
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#define CONC_dSRCIO_OFF 0x10 /* I/O ctl/stat/data for SRC RAM */
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#define CONC_dCODECCTL_OFF 0x14 /* CODEC control - u32_t read/write */
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#define CONC_wNMISTAT_OFF 0x18 /* Legacy NMI status */
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#define CONC_bNMIENA_OFF 0x1a /* Legacy NMI enable */
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#define CONC_bNMICTL_OFF 0x1b /* Legacy control */
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#define CONC_bSERFMT_OFF 0x20 /* Serial device format */
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#define CONC_bSERCTL_OFF 0x21 /* Serial device control */
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#define CONC_bSKIPC_OFF 0x22 /* DAC skip count reg */
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#define CONC_wSYNIC_OFF 0x24 /* Synth int count in sample frames */
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#define CONC_wSYNCIC_OFF 0x26 /* Synth current int count */
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#define CONC_wDACIC_OFF 0x28 /* DAC int count in sample frames */
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#define CONC_wDACCIC_OFF 0x2a /* DAC current int count */
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#define CONC_wADCIC_OFF 0x2c /* ADC int count in sample frames */
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#define CONC_wADCCIC_OFF 0x2e /* ADC current int count */
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#define CONC_MEMBASE_OFF 0x30 /* Memory window base - 16 byte window */
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/* Concert memory page-banked register offset defines */
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#define CONC_dSYNPADDR_OFF 0x30 /* Synth host frame PCI phys addr */
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#define CONC_wSYNFC_OFF 0x34 /* Synth host frame count in u32_t'S */
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#define CONC_wSYNCFC_OFF 0x36 /* Synth host current frame count */
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#define CONC_dDACPADDR_OFF 0x38 /* DAC host frame PCI phys addr */
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#define CONC_wDACFC_OFF 0x3c /* DAC host frame count in u32_t'S */
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#define CONC_wDACCFC_OFF 0x3e /* DAC host current frame count */
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#define CONC_dADCPADDR_OFF 0x30 /* ADC host frame PCI phys addr */
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#define CONC_wADCFC_OFF 0x34 /* ADC host frame count in u32_t'S */
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#define CONC_wADCCFC_OFF 0x36 /* ADC host current frame count */
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/* memory page number defines */
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#define CONC_SYNRAM_PAGE 0x00 /* Synth host/serial I/F RAM */
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#define CONC_DACRAM_PAGE 0x04 /* DAC host/serial I/F RAM */
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#define CONC_ADCRAM_PAGE 0x08 /* ADC host/serial I/F RAM */
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#define CONC_SYNCTL_PAGE 0x0c /* Page bank for synth host control */
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#define CONC_DACCTL_PAGE 0x0c /* Page bank for DAC host control */
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#define CONC_ADCCTL_PAGE 0x0d /* Page bank for ADC host control */
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#define CONC_FIFO0_PAGE 0x0e /* page 0 of UART "FIFO" (rx stash) */
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#define CONC_FIFO1_PAGE 0x0f /* page 1 of UART "FIFO" (rx stash) */
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/* bits for Interrupt/Chip Select Control Register (offset 0x00)*/
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#define DAC1_EN_BIT bit(6)
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#define DAC2_EN_BIT bit(5)
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#define ADC1_EN_BIT bit(4)
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#define SYNC_RES_BIT bit(14)
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/* bits for Interrupt/Chip Select Status Register (offset 0x04)*/
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#define DAC1_INT_STATUS_BIT bit(2)
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#define DAC2_INT_STATUS_BIT bit(1)
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#define ADC1_INT_STATUS_BIT bit(0)
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/* some bits for Serial Interface Control Register (CONC_bSERFMT_OFF 20H) */
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#define DAC1_STEREO_BIT bit(0) /* stereo or mono format */
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#define DAC1_16_8_BIT bit(1) /* 16 or 8 bit format */
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#define DAC2_STEREO_BIT bit(2)
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#define DAC2_16_8_BIT bit(3)
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#define ADC1_STEREO_BIT bit(4)
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#define ADC1_16_8_BIT bit(5)
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#define DAC1_INT_EN_BIT bit(8) /* interupt enable bits */
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#define DAC2_INT_EN_BIT bit(9)
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#define ADC1_INT_EN_BIT bit(10)
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#define DAC1_PAUSE_BIT bit(11)
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#define DAC2_PAUSE_BIT bit(12)
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/* Some return values */
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#define SRC_SUCCESS 0
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#define CONC_SUCCESS 0
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/* Timeout waiting for: */
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#define SRC_ERR_NOT_BUSY_TIMEOUT -1 /* SRC not busy */
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#define CONC_ERR_NO_PCI_BIOS -2
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#define CONC_ERR_DEVICE_NOT_FOUND -3
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#define CONC_ERR_SPDIF_NOT_AVAIL -4
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#define CONC_ERR_SPDIF_ROUTING_NOT_AVAIL -5
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#define CONC_ERR_4SPEAKER_NOT_AVAIL -6
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#define CONC_ERR_ECHO_NOT_AVAIL -7
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typedef struct {
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u32_t stereo;
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u16_t sample_rate;
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u32_t nr_of_bits;
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u32_t sign;
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u32_t busy;
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u32_t fragment_size;
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} aud_sub_dev_conf_t;
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/* Some defaults for the aud_sub_dev_conf_t*/
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#define DEFAULT_RATE 44100 /* Sample rate */
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#define DEFAULT_NR_OF_BITS 16 /* Nr. of bits per sample per channel*/
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#define DEFAULT_SIGNED 0 /* 0 = unsigned, 1 = signed */
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#define DEFAULT_STEREO 1 /* 0 = mono, 1 = stereo */
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#define MAX_RATE 44100 /* Max sample speed in KHz */
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#define MIN_RATE 4000 /* Min sample speed in KHz */
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typedef struct DEVSTRUCT {
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char* name;
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u16_t v_id; /* vendor id */
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u16_t d_id; /* device id */
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u32_t devind; /* minix pci device id, for pci configuration space */
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u32_t base; /* changed to 32 bits */
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char irq;
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char revision;/* version of the device */
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} DEV_STRUCT;
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#define bit(n) 1UL << n
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#endif /* ES1371_H */
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