276 lines
15 KiB
C
276 lines
15 KiB
C
struct omap_mmchs_registers;
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struct omap_mmchs {
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vir_bytes io_base;
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vir_bytes io_size;
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phys_bytes hw_base;/* HW address */
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int irq_nr;
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struct omap_mmchs_registers * regs;
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};
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struct omap_mmchs_registers {
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/* SD system configuration */
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vir_bytes SYSCONFIG;
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/* SD system status */
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vir_bytes SYSSTATUS;
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/* Configuration (functional mode,card initialization etc) */
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vir_bytes CON;
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/* Transfer length configuration */
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vir_bytes BLK;
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/* Command argument bit 38-8 of command format*/
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vir_bytes ARG;
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/* Command and transfer mode */
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vir_bytes CMD;
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/* SDMA System address */
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vir_bytes SDMASA;
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/* Command response 0 and 1 */
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vir_bytes RSP10;
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/* Command response 2 and 3 */
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vir_bytes RSP32;
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/* Command response 4 and 5 */
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vir_bytes RSP54;
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/* Command response 6 and 7 */
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vir_bytes RSP76;
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/* Data register */
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vir_bytes DATA;
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/* Present state */
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vir_bytes PSTATE;
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/* Host control(power ,wake-up and transfer) */
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vir_bytes HCTL;
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/* SD System control (reset,clocks and timeout) */
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vir_bytes SYSCTL;
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/* SD Interrupt status */
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vir_bytes SD_STAT;
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/* SD Interrupt Enable register */
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vir_bytes IE;
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/* SD Interrupt Signal Enable register */
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vir_bytes ISE;
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/* Capabilities of the host controller */
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vir_bytes CAPA;
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/* Current capabilities of the host controller */
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vir_bytes CUR_CAPA;
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};
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/* version used on the AM335x */
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static struct omap_mmchs_registers regs_v1 = {
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.SYSCONFIG = 0x110,
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.SYSSTATUS = 0x114,
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.CON = 0x12c,
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.BLK = 0x204,
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.ARG = 0x208,
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.CMD = 0x20c,
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.SDMASA = 0x200,
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.RSP10 = 0x210,
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.RSP32 = 0x214,
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.RSP54 = 0x218,
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.RSP76 = 0x21c,
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.DATA = 0x220,
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.PSTATE = 0x224,
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.HCTL = 0x228,
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.SYSCTL = 0x22c,
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.SD_STAT = 0x230,
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.IE = 0x234,
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.ISE = 0x238,
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.CAPA = 0x240,
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.CUR_CAPA = 0x248,
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};
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/* version used on the DM37xx */
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/* DM and AM have the same register but shifted by 0x100. */
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static struct omap_mmchs_registers regs_v0 = {
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.SYSCONFIG = 0x010,
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.SYSSTATUS = 0x014,
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.CON = 0x02c,
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.BLK = 0x104,
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.ARG = 0x108,
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.CMD = 0x10c,
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.SDMASA = 0x100,
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.RSP10 = 0x110,
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.RSP32 = 0x114,
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.RSP54 = 0x118,
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.RSP76 = 0x11c,
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.DATA = 0x120,
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.PSTATE = 0x124,
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.HCTL = 0x128,
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.SYSCTL = 0x12c,
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.SD_STAT = 0x130,
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.IE = 0x134,
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.ISE = 0x138,
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.CAPA = 0x140,
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.CUR_CAPA = 0x148,
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};
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#define MMCHS_SD_SYSCONFIG_AUTOIDLE (0x1 << 0) /* Internal clock gating strategy */
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#define MMCHS_SD_SYSCONFIG_AUTOIDLE_DIS (0x0 << 0) /* Clocks are free running */
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#define MMCHS_SD_SYSCONFIG_AUTOIDLE_EN (0x1 << 0) /* Automatic clock gating strategy */
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#define MMCHS_SD_SYSCONFIG_SOFTRESET (0x1 << 1) /* Software reset bit writing */
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#define MMCHS_SD_SYSCONFIG_ENAWAKEUP (0x1 << 2) /* Wake-up feature control */
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#define MMCHS_SD_SYSCONFIG_ENAWAKEUP_DIS (0x0 << 2) /* Disable wake-up capability */
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#define MMCHS_SD_SYSCONFIG_ENAWAKEUP_EN (0x1 << 2) /* Enable wake-up capability */
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#define MMCHS_SD_SYSCONFIG_SIDLEMODE (0x3 << 3) /* Power management */
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#define MMCHS_SD_SYSCONFIG_SIDLEMODE_UNCONDITIONAL (0x0 << 3) /* Go into idle mode unconditionally upon request */
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#define MMCHS_SD_SYSCONFIG_SIDLEMODE_IGNORE (0x1 << 3) /* Ignore ILDE requests */
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#define MMCHS_SD_SYSCONFIG_SIDLEMODE_IDLE (0x2 << 3) /* Acknowledge IDLE request switch to wake-up mode */
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#define MMCHS_SD_SYSCONFIG_SIDLEMODE_SMART_IDLE (0x3 << 3) /* Smart-idle */
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#define MMCHS_SD_SYSCONFIG_CLOCKACTIVITY (0x3 << 8) /* Clock activity during wake-up */
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#define MMCHS_SD_SYSCONFIG_CLOCKACTIVITY_OFF (0x0 << 8) /* Interface and functional clock can be switched off */
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#define MMCHS_SD_SYSCONFIG_CLOCKACTIVITY_IF (0x1 << 8) /* Only Interface clock (functional can be switched off*/
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#define MMCHS_SD_SYSCONFIG_CLOCKACTIVITY_FUNC (0x2 << 8) /* Only Functional clock (interface clock can be switched off) */
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#define MMCHS_SD_SYSCONFIG_CLOCKACTIVITY_BOOTH (0x3 << 8) /* Booth the interface and functional clock are maintained */
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#define MMCHS_SD_SYSCONFIG_STANDBYMODE (0x3 << 12) /* Configuration for standby */
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#define MMCHS_SD_SYSCONFIG_STANDBYMODE_FORCE_STANDBY (0x0 << 12) /* Force standby mode upon idle request*/
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#define MMCHS_SD_SYSCONFIG_STANDBYMODE_NO_STANDBY (0x1 << 12) /* Never go into standby mode */
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#define MMCHS_SD_SYSCONFIG_STANDBYMODE_WAKEUP_INTERNAL (0x2 << 12) /* Go into wake-up mode based on internal knowledge */
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#define MMCHS_SD_SYSCONFIG_STANDBYMODE_WAKEUP_SMART (0x3 << 12) /* Go info wake-up mode when possible */
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#define MMCHS_SD_SYSSTATUS_RESETDONE 0x01
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#define MMCHS_SD_CON_DW8 (0x1 << 5) /* 8-bit mode MMC select , For SD clear this bit */
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#define MMCHS_SD_CON_DW8_1BIT (0x0 << 5) /* 1 or 4 bits data width configuration(also set SD_HCTL) */
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#define MMCHS_SD_CON_DW8_8BITS (0x1 << 5) /* 8 bits data width configuration */
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#define MMCHS_SD_CON_INIT (0x1 << 1) /* Send initialization stream (all cards) */
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#define MMCHS_SD_CON_INIT_NOINIT (0x0 << 1) /* Do nothing */
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#define MMCHS_SD_CON_INIT_INIT (0x1 << 1) /* Send initialization stream */
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#define MMCHS_SD_CON_OD (0x1 << 0) /* Card open drain mode (MMC cards only) */
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#define MMCHS_SD_CON_OD_PP (0x0 << 0) /* No open drain (push-pull). */
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#define MMCHS_SD_CON_OD_OD (0x1 << 0) /* Open drain */
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#define MMCHS_SD_BLK_NBLK (0xffffu << 16) /* Block count for the current transfer */
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#define MMCHS_SD_BLK_BLEN (0xfff << 0) /* Transfer block size */
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#define MMCHS_SD_BLK_BLEN_NOTRANSFER (0x0 << 0) /* No transfer */
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#define MMCHS_SD_CMD_INDX (0x3f << 24) /* Command index */
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#define MMCHS_SD_CMD_INDX_CMD(x) (x << 24) /* MMC command index binary encoded values from 0 to 63 */
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#define MMCHS_SD_ARG_MASK (0xffffffffu) /* Mask everything */
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#define MMCHS_SD_ARG_CMD8_VHS (0x1 << (16 - 8)) /* Voltage between 2.7 and 3.6 v*/
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#define MMCHS_SD_ARG_CMD8_CHECK_PATTERN (0xaa <<(8 - 8)) /* 10101010b pattern */
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#define MMCHS_SD_CMD_TYPE (0x3 << 22) /* Command type. */
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#define MMCHS_SD_CMD_TYPE_OTHER (0x0 << 22) /* Other type of commands (like go idle) */
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#define MMCHS_SD_CMD_TYPE_BUS_SUSPEND (0x1 << 22) /* Upon CMD52 "Bus Suspend" operation */
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#define MMCHS_SD_CMD_TYPE_FUNCTION_SELECT (0x2 << 22) /* Upon CMD52 "Function Select" operation */
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#define MMCHS_SD_CMD_TYPE_IOABORT (0x3 << 22) /* Upon CMD12 and CMD21 "I/O Abort */
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#define MMCHS_SD_CMD_DP (0x1 << 21) /* Data present select */
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#define MMCHS_SD_CMD_DP_DATA (0x1 << 21) /* Additional data is present on the data lines */
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#define MMCHS_SD_CMD_DP_NODATA (0x0 << 21) /* No additional data is present on the data lines */
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#define MMCHS_SD_CMD_CICE (0x1 << 20) /* Command index response check enable */
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#define MMCHS_SD_CMD_CICE_ENABLE (0x1 << 20) /* Enable index check response */
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#define MMCHS_SD_CMD_CICE_DISABLE (0x0 << 20) /* Disable index check response */
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#define MMCHS_SD_CMD_CCCE (0x1 << 19) /* Command CRC7 Check enable on responses*/
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#define MMCHS_SD_CMD_CCCE_ENABLE (0x1 << 19) /* Enable CRC7 Check on response */
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#define MMCHS_SD_CMD_CCCE_DISABLE (0x0 << 19) /* Disable CRC7 Check on response */
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#define MMCHS_SD_CMD_RSP_TYPE (0x3 << 16) /* Response type */
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#define MMCHS_SD_CMD_RSP_TYPE_NO_RESP (0x0 << 16) /* No response */
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#define MMCHS_SD_CMD_RSP_TYPE_136B (0x1 << 16) /* Response length 136 bits */
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#define MMCHS_SD_CMD_RSP_TYPE_48B (0x2 << 16) /* Response length 48 bits */
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#define MMCHS_SD_CMD_RSP_TYPE_48B_BUSY (0x3 << 16) /* Response length 48 bits with busy after response */
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#define MMCHS_SD_CMD_MSBS (0x1 << 5) /* Multi/Single block select */
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#define MMCHS_SD_CMD_MSBS_SINGLE (0x0 << 5) /* Single block mode */
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#define MMCHS_SD_CMD_MSBS_MULTI (0x0 << 5) /* Multi block mode */
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#define MMCHS_SD_CMD_DDIR (0x1 << 4) /* Data transfer direction */
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#define MMCHS_SD_CMD_DDIR_READ (0x1 << 4) /* Data read (card to host) */
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#define MMCHS_SD_CMD_DDIR_WRITE (0x0 << 4) /* Data write (host to card) */
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#define MMCHS_SD_CMD_ACEN (0x1 << 2) /* Auto CMD12 Enable */
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#define MMCHS_SD_CMD_ACEN_DIS (0x0 << 2) /* Auto CMD12 Disable */
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#define MMCHS_SD_CMD_ACEN_EN (0x1 << 2) /* Auto CMD12 Enable */
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#define MMCHS_SD_CMD_BCE (0x1 << 1) /* Block Count Enable(for multi block transfer) */
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#define MMCHS_SD_CMD_BCE_DIS (0x0 << 1) /* Disabled block count for infinite transfer*/
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#define MMCHS_SD_CMD_BCE_EN (0x1 << 1) /* Enabled for multi block transfer with know amount of blocks */
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#define MMCHS_SD_CMD_DE (0x1 << 0) /* DMA enable */
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#define MMCHS_SD_CMD_DE_DIS (0x0 << 0) /* Disable DMA */
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#define MMCHS_SD_CMD_DE_EN (0x1 << 0) /* Enable DMA */
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#define MMCHS_SD_CMD_MASK ~(0x1 << 30 | 0x1 << 31 | 0x1 << 18 | 0x1 <<3) /* bits 30 , 31 and 18 are reserved */
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#define MMCHS_SD_PSTATE_CI (0x1 << 16) /* Card Inserted */
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#define MMCHS_SD_PSTATE_CI_INSERTED (0x1 << 16) /* Card Inserted is inserted*/
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#define MMCHS_SD_PSTATE_BRE (0x1 << 11) /* Buffer read enable */
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#define MMCHS_SD_PSTATE_BRE_DIS (0x0 << 11) /* Read BLEN bytes disabled*/
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#define MMCHS_SD_PSTATE_BRE_EN (0x1 << 11) /* Read BLEN bytes enabled*/
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#define MMCHS_SD_PSTATE_BWE (0x1 << 10) /* Buffer Write enable */
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#define MMCHS_SD_PSTATE_BWE_DIS (0x0 << 10) /* There is no room left in the buffer to write BLEN bytes of data */
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#define MMCHS_SD_PSTATE_BWE_EN (0x1 << 10) /* There is enough space in the buffer to write BLEN bytes of data*/
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#define MMCHS_SD_PSTATE_DATI (0x1 << 1) /* Command inhibit (mmc_dat) */
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#define MMCHS_SD_PSTATE_CMDI (0x1 << 0) /* Command inhibit (mmc_cmd) */
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#define MMCHS_SD_HCTL_DTW (0x1 << 1) /*Data transfer width.(must be set after a successful ACMD6) */
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#define MMCHS_SD_HCTL_DTW_1BIT (0x0 << 1) /*1 bit transfer with */
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#define MMCHS_SD_HCTL_DTW_4BIT (0x1 << 1) /*4 bit transfer with */
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#define MMCHS_SD_HCTL_SDBP (0x1 << 8) /*SD bus power */
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#define MMCHS_SD_HCTL_SDBP_OFF (0x0 << 8) /*SD Power off (start card detect?) */
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#define MMCHS_SD_HCTL_SDBP_ON (0x1 << 8) /*SD Power on (start card detect?) */
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#define MMCHS_SD_HCTL_SDVS (0x7 << 9) /*SD bus voltage select */
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#define MMCHS_SD_HCTL_SDVS_VS18 (0x5 << 9) /*1.8 V */
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#define MMCHS_SD_HCTL_SDVS_VS30 (0x6 << 9) /*3.0 V */
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#define MMCHS_SD_HCTL_SDVS_VS33 (0x7 << 9) /*3.3 V */
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#define MMCHS_SD_HCTL_IWE (0x1 << 24)/* wake-up event on SD interrupt */
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#define MMCHS_SD_HCTL_IWE_DIS (0x0 << 24)/* Disable wake-up on SD interrupt */
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#define MMCHS_SD_HCTL_IWE_EN (0x1 << 24)/* Enable wake-up on SD interrupt */
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#define MMCHS_SD_SYSCTL_CLKD (0x3ff << 6) /* 10 bits clock frequency select */
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#define MMCHS_SD_SYSCTL_SRD (0x1 << 26) /* Soft reset for mmc_dat line */
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#define MMCHS_SD_SYSCTL_SRC (0x1 << 25) /* Soft reset for mmc_cmd line */
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#define MMCHS_SD_SYSCTL_SRA (0x1 << 24) /* Soft reset all (host controller) */
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#define MMCHS_SD_SYSCTL_ICE (0x1 << 0) /* Internal clock enable register */
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#define MMCHS_SD_SYSCTL_ICE_DIS (0x0 << 0) /* Disable internal clock */
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#define MMCHS_SD_SYSCTL_ICE_EN (0x1 << 0) /* Enable internal clock */
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#define MMCHS_SD_SYSCTL_ICS (0x1 << 1) /* Internal clock stable register */
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#define MMCHS_SD_SYSCTL_ICS_UNSTABLE (0x0 << 1) /* Internal clock is unstable */
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#define MMCHS_SD_SYSCTL_ICS_STABLE (0x1 << 1) /* Internal clock is stable */
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#define MMCHS_SD_SYSCTL_CEN (0x1 << 2) /* Card lock enable provide clock to the card */
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#define MMCHS_SD_SYSCTL_CEN_DIS (0x0 << 2) /* Internal clock is unstable */
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#define MMCHS_SD_SYSCTL_CEN_EN (0x1 << 2) /* Internal clock is stable */
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#define MMCHS_SD_SYSCTL_DTO (0xf << 16) /* Data timeout counter */
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#define MMCHS_SD_SYSCTL_DTO_2POW13 (0x0 << 16) /* TCF x 2^13 */
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#define MMCHS_SD_SYSCTL_DTO_2POW14 (0x1 << 16) /* TCF x 2^14 */
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#define MMCHS_SD_SYSCTL_DTO_2POW20 (0x7 << 16) /* TCF x 2^20 */
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#define MMCHS_SD_SYSCTL_DTO_2POW27 (0xe << 16) /* TCF x 2^27 */
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#define MMCHS_SD_STAT_CERR (0x1 << 28) /* card error */
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#define MMCHS_SD_STAT_DEB (0x1 << 22) /* data end bit error */
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#define MMCHS_SD_STAT_DCRC (0x1 << 21) /* data CRC error */
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#define MMCHS_SD_STAT_DTO (0x1 << 20) /* data timeout error */
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#define MMCHS_SD_STAT_CIE (0x1 << 19) /* command index error */
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#define MMCHS_SD_STAT_CEB (0x1 << 18) /* command end bit error */
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#define MMCHS_SD_STAT_CCRC (0x1 << 17) /* command CRC error */
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#define MMCHS_SD_STAT_CTO (0x1 << 16) /* command timeout error */
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#define MMCHS_SD_STAT_ERRI (0x01 << 15) /* Error interrupt */
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#define MMCHS_SD_STAT_ERROR_MASK (0xff << 15 | 0x3 << 24 | 0x03 << 28)
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#define MMCHS_SD_STAT_BRR (0x1 << 5) /* Buffer Read ready */
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#define MMCHS_SD_STAT_BWR (0x1 << 4) /* Buffer Write ready */
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#define MMCHS_SD_STAT_CC (0x1 << 0) /* Command complete status */
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#define MMCHS_SD_STAT_CC_UNRAISED (0x0 << 0) /* Command not completed */
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#define MMCHS_SD_STAT_CC_RAISED (0x1 << 0) /* Command completed */
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#define MMCHS_SD_STAT_TC (0x1 << 1) /* Transfer complete status */
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#define MMCHS_SD_STAT_TC_UNRAISED (0x0 << 1) /* Transfer not completed */
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#define MMCHS_SD_STAT_TC_RAISED (0x1 << 1) /* Transfer completed */
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#define MMCHS_SD_IE_ERROR_MASK (0xff << 15 | 0x3 << 24 | 0x03 << 28)
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#define MMCHS_SD_IE_CC_ENABLE (0x1 << 0) /* Command complete interrupt enable */
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#define MMCHS_SD_IE_CC_ENABLE_ENABLE (0x1 << 0) /* Command complete Interrupts are enabled */
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#define MMCHS_SD_IE_CC_ENABLE_CLEAR (0x1 << 0) /* Clearing is done by writing a 0x1 */
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#define MMCHS_SD_IE_TC_ENABLE (0x1 << 1) /* Transfer complete interrupt enable */
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#define MMCHS_SD_IE_TC_ENABLE_ENABLE (0x1 << 1) /* Transfer complete Interrupts are enabled */
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#define MMCHS_SD_IE_TC_ENABLE_CLEAR (0x1 << 1) /* Clearing TC is done by writing a 0x1 */
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#define MMCHS_SD_IE_BRR_ENABLE (0x1 << 5) /* Buffer read ready interrupt */
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#define MMCHS_SD_IE_BRR_ENABLE_DISABLE (0x0 << 5) /* Buffer read ready interrupt disable */
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#define MMCHS_SD_IE_BRR_ENABLE_ENABLE (0x1 << 5) /* Buffer read ready interrupt enable */
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#define MMCHS_SD_IE_BRR_ENABLE_CLEAR (0x1 << 5) /* Buffer read ready interrupt clear */
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#define MMCHS_SD_IE_BWR_ENABLE (0x1 << 4) /* Buffer write ready interrupt */
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#define MMCHS_SD_IE_BWR_ENABLE_DISABLE (0x0 << 4) /* Buffer write ready interrupt disable */
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#define MMCHS_SD_IE_BWR_ENABLE_ENABLE (0x1 << 4) /* Buffer write ready interrupt enable */
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#define MMCHS_SD_IE_BWR_ENABLE_CLEAR (0x1 << 4) /* Buffer write ready interrupt clear */
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#define MMCHS_SD_CAPA_VS_MASK (0x7 << 24 ) /* voltage mask */
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#define MMCHS_SD_CAPA_VS18 (0x01 << 26 ) /* 1.8 volt */
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#define MMCHS_SD_CAPA_VS30 (0x01 << 25 ) /* 3.0 volt */
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#define MMCHS_SD_CAPA_VS33 (0x01 << 24 ) /* 3.3 volt */
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