#include #include #include #include #include #include /* Register Addresses */ #define CHIPID_REG 0x00 #define PPATH_REG 0x01 #define INT_REG 0x02 #define CHGCONFIG0_REG 0x03 #define CHGCONFIG1_REG 0x04 #define CHGCONFIG2_REG 0x05 #define CHGCONFIG3_REG 0x06 #define WLEDCTRL1_REG 0x07 #define WLEDCTRL2_REG 0x08 #define MUXCTRL_REG 0x09 #define STATUS_REG 0x0a #define PASSWORD_REG 0x0b #define PGOOD_REG 0x0c #define DEFPG_REG 0x0d #define DEFDCDC1_REG 0x0e #define DEFDCDC2_REG 0x0f #define DEFDCDC3_REG 0x10 #define DEFSLEW_REG 0x11 #define DEFLDO1_REG 0x12 #define DEFLDO2_REG 0x13 #define DEFLS1_REG 0x14 #define DEFLS2_REG 0x15 #define ENABLE_REG 0x16 /* no documented register at 0x17 */ #define DEFUVLO_REG 0x18 #define SEQ1_REG 0x19 #define SEQ2_REG 0x1a #define SEQ3_REG 0x1b #define SEQ4_REG 0x1c #define SEQ5_REG 0x1d #define SEQ6_REG 0x1e /* Bits and Masks */ /* * CHIP masks - CHIPID_REG[7:4] */ #define TPS65217A_CHIP_MASK 0x70 #define TPS65217B_CHIP_MASK 0xf0 #define TPS65217C_CHIP_MASK 0xe0 #define TPS65217D_CHIP_MASK 0x60 /* * Interrupt Enable/Disable Bits/Masks - INT_REG[6:4] * 0=Enable 1=Disable | Default mask: Disable ACM, USBM ~ Enable only PBM */ #define PBM_INT_DIS_BIT 6 #define ACM_INT_DIS_BIT 5 #define USBM_INT_DIS_BIT 4 #define DEFAULT_INT_MASK ((1< 0) { log_warn(&log, "Invalid slave address for device, expecting 0x24\n"); return EXIT_FAILURE; } sef_local_startup(); while (TRUE) { /* Receive Message */ r = sef_receive_status(ANY, &m, &ipc_status); if (r != OK) { log_warn(&log, "sef_receive_status() failed\n"); continue; } log_trace(&log, "Got a message 0x%x from 0x%x\n", m.m_type, m.m_source); if (is_ipc_notify(ipc_status)) { switch (m.m_source) { case DS_PROC_NR: /* bus driver changed state, update endpoint */ i2cdriver_handle_bus_update(&bus_endpoint, bus, address); break; case HARDWARE: intr_handler(); break; default: break; } /* Do not reply to notifications. */ continue; } log_warn(&log, "Ignoring message 0x%x from 0x%x\n", m.m_type, m.m_source); } return 0; }