Fix for usbd-usb_storage pairing and URB handling. Additional cleanup.
This commit is contained in:
parent
9f2204a8ad
commit
f73cacc767
8 changed files with 168 additions and 141 deletions
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@ -27,7 +27,7 @@ static int hcd_enumerate(hcd_device_state *);
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static int hcd_get_device_descriptor(hcd_device_state *);
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static int hcd_get_device_descriptor(hcd_device_state *);
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static int hcd_set_address(hcd_device_state *, int);
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static int hcd_set_address(hcd_device_state *, int);
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static int hcd_get_descriptor_tree(hcd_device_state *);
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static int hcd_get_descriptor_tree(hcd_device_state *);
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static int hcd_set_configuration(hcd_device_state *, int);
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static int hcd_set_configuration(hcd_device_state *, hcd_reg1);
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static int hcd_handle_urb(hcd_device_state *);
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static int hcd_handle_urb(hcd_device_state *);
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static int hcd_control_urb(hcd_device_state *);
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static int hcd_control_urb(hcd_device_state *);
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static int hcd_non_control_urb(hcd_device_state *, int);
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static int hcd_non_control_urb(hcd_device_state *, int);
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@ -196,6 +196,12 @@ hcd_enumerate(hcd_device_state * this_device)
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return EXIT_FAILURE;
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return EXIT_FAILURE;
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}
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}
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/* Default MaxPacketSize, based on speed */
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if (HCD_SPEED_LOW == this_device->speed)
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this_device->max_packet_size = HCD_LS_MAXPACKETSIZE;
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else
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this_device->max_packet_size = HCD_HS_MAXPACKETSIZE;
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/* Get device descriptor */
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/* Get device descriptor */
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if (EXIT_SUCCESS != hcd_get_device_descriptor(this_device)) {
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if (EXIT_SUCCESS != hcd_get_device_descriptor(this_device)) {
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USB_MSG("Failed to get device descriptor");
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USB_MSG("Failed to get device descriptor");
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@ -415,7 +421,7 @@ hcd_get_descriptor_tree(hcd_device_state * this_device)
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* hcd_set_configuration *
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* hcd_set_configuration *
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*===========================================================================*/
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*===========================================================================*/
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static int
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static int
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hcd_set_configuration(hcd_device_state * this_device, int configuration)
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hcd_set_configuration(hcd_device_state * this_device, hcd_reg1 configuration)
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{
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{
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hcd_ctrlrequest setup;
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hcd_ctrlrequest setup;
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@ -454,7 +460,7 @@ hcd_handle_urb(hcd_device_state * this_device)
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USB_ASSERT(NULL != urb, "NULL URB given");
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USB_ASSERT(NULL != urb, "NULL URB given");
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/* TODO: One device only */
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/* TODO: One device only */
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USB_ASSERT((void *)this_device != (void *)urb->dev,
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USB_ASSERT((void *)this_device == (void *)urb->dev,
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"Unknown device for URB");
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"Unknown device for URB");
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switch (urb->type) {
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switch (urb->type) {
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@ -536,7 +542,12 @@ hcd_control_urb(hcd_device_state * this_device)
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return EXIT_FAILURE;
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return EXIT_FAILURE;
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}
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}
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/* TODO: Calling memcpy may be removed when writing directly to URB */
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/* Put what was read back into URB */
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memcpy(urb->data, this_device->buffer, this_device->data_len);
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urb->actual_length = (unsigned int)this_device->data_len;
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urb->status = EXIT_SUCCESS;
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urb->status = EXIT_SUCCESS;
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return EXIT_SUCCESS;
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return EXIT_SUCCESS;
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}
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}
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@ -563,8 +574,8 @@ hcd_non_control_urb(hcd_device_state * this_device, int type)
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return EXIT_FAILURE;
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return EXIT_FAILURE;
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}
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}
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if ((UE_GET_ADDR(urb->endpoint) >= 16) ||
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if ((UE_GET_ADDR(urb->endpoint) >= HCD_TOTAL_EP) ||
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(UE_GET_ADDR(urb->endpoint) <= 0)) {
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(UE_GET_ADDR(urb->endpoint) <= HCD_DEFAULT_EP)) {
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USB_MSG("Illegal EP number");
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USB_MSG("Illegal EP number");
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return EXIT_FAILURE;
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return EXIT_FAILURE;
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}
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}
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@ -594,7 +605,7 @@ hcd_non_control_urb(hcd_device_state * this_device, int type)
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/* Assign to data request structure */
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/* Assign to data request structure */
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request.endpoint = urb->endpoint;
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request.endpoint = urb->endpoint;
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request.direction = urb->direction;
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request.direction = urb->direction;
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request.size = (int)urb->size;
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request.data_left = (int)urb->size;
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request.data = urb->data;
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request.data = urb->data;
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request.interval = urb->interval;
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request.interval = urb->interval;
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@ -633,7 +644,9 @@ hcd_non_control_urb(hcd_device_state * this_device, int type)
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}
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}
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/* Transfer successfully completed */
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/* Transfer successfully completed */
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urb->actual_length = urb->size - request.data_left;
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urb->status = EXIT_SUCCESS;
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urb->status = EXIT_SUCCESS;
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return EXIT_SUCCESS;
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return EXIT_SUCCESS;
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}
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}
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@ -646,15 +659,18 @@ hcd_setup_packet(hcd_device_state * this_device, hcd_ctrlrequest * setup)
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{
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{
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hcd_driver_state * d;
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hcd_driver_state * d;
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hcd_reg1 * current_byte;
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hcd_reg1 * current_byte;
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int expected_len;
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int rx_len;
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int received_len;
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DEBUG_DUMP;
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DEBUG_DUMP;
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/* Should have been set at enumeration or with default values */
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USB_ASSERT(this_device->max_packet_size > 0,
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"Illegal MaxPacketSize for EP0");
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/* Initially... */
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/* Initially... */
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d = this_device->driver;
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d = this_device->driver;
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expected_len = (int)setup->wLength;
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current_byte = this_device->buffer; /* Start reading into this */
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current_byte = this_device->buffer;
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this_device->data_len = 0; /* Nothing read yet */
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/* Send setup packet */
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/* Send setup packet */
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d->setup_stage(d->private_data, setup);
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d->setup_stage(d->private_data, setup);
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@ -669,16 +685,14 @@ hcd_setup_packet(hcd_device_state * this_device, hcd_ctrlrequest * setup)
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return EXIT_FAILURE;
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return EXIT_FAILURE;
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/* For data packets... */
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/* For data packets... */
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if (expected_len > 0) {
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if (setup->wLength > 0) {
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/* TODO: magic number */
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/* TODO: magic number */
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/* ...IN data packets */
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/* ...IN data packets */
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if (setup->bRequestType & 0x80) {
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if (setup->bRequestType & 0x80) {
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/* What was received until now */
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for(;;) {
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this_device->data_len = 0;
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do {
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/* Try getting data */
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/* Try getting data */
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d->in_data_stage(d->private_data);
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d->in_data_stage(d->private_data);
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@ -695,24 +709,30 @@ hcd_setup_packet(hcd_device_state * this_device, hcd_ctrlrequest * setup)
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return EXIT_FAILURE;
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return EXIT_FAILURE;
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/* Read data received as response */
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/* Read data received as response */
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received_len = d->read_data(d->private_data,
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rx_len = d->read_data(d->private_data,
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current_byte, 0);
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current_byte, HCD_DEFAULT_EP);
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/* Data reading should always yield positive
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/* Increment */
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* results for proper setup packet */
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current_byte += rx_len;
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if (received_len > 0) {
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this_device->data_len += rx_len;
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/* Try next packet */
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this_device->data_len += received_len;
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current_byte += received_len;
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} else
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return EXIT_FAILURE;
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} while (expected_len > this_device->data_len);
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/* If full max sized packet was read... */
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if (rx_len == (int)this_device->max_packet_size)
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/* ...try reading next packet even if
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* zero bytes may be received */
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continue;
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/* Should be exactly what we requested, no more */
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/* If less than max data was read... */
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if (this_device->data_len != expected_len) {
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if (rx_len < (int)this_device->max_packet_size)
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USB_MSG("Received more data than expected");
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/* ...it must have been
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return EXIT_FAILURE;
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* the last packet */
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break;
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/* Unreachable during normal operation */
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USB_MSG("rx_len: %d; max_packet_size: %d",
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rx_len, this_device->max_packet_size);
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USB_ASSERT(0, "Illegal state of data "
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"receive operation");
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}
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}
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} else {
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} else {
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@ -755,7 +775,7 @@ hcd_setup_packet(hcd_device_state * this_device, hcd_ctrlrequest * setup)
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return EXIT_FAILURE;
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return EXIT_FAILURE;
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/* Read zero data from response to clear registers */
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/* Read zero data from response to clear registers */
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if (0 != d->read_data(d->private_data, NULL, 0))
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if (0 != d->read_data(d->private_data, NULL, HCD_DEFAULT_EP))
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return EXIT_FAILURE;
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return EXIT_FAILURE;
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}
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}
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@ -775,13 +795,18 @@ hcd_data_transfer(hcd_device_state * this_device, hcd_datarequest * request)
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DEBUG_DUMP;
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DEBUG_DUMP;
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USB_ASSERT((hcd_reg1)(UE_GET_ADDR(request->endpoint)) <= HCD_LAST_EP,
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"Invalid EP number");
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USB_ASSERT((hcd_reg1)(this_device->address) <= HCD_LAST_ADDR,
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"Invalid device address");
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/* Initially... */
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/* Initially... */
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d = this_device->driver;
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d = this_device->driver;
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/* Set parameters for further communication */
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/* Set parameters for further communication */
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d->setup_device(d->private_data,
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d->setup_device(d->private_data,
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request->endpoint,
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(hcd_reg1)request->endpoint,
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this_device->address);
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(hcd_reg1)this_device->address);
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/* TODO: broken USB_IN... constants */
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/* TODO: broken USB_IN... constants */
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if (1 == request->direction) {
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if (1 == request->direction) {
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@ -803,46 +828,34 @@ hcd_data_transfer(hcd_device_state * this_device, hcd_datarequest * request)
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/* Read data received as response */
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/* Read data received as response */
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transfer_len = d->read_data(d->private_data,
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transfer_len = d->read_data(d->private_data,
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(hcd_reg1 *)request->data,
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(hcd_reg1 *)request->data,
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request->endpoint);
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(hcd_reg1)request->endpoint);
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request->size -= transfer_len;
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request->data_left -= transfer_len;
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request->data += transfer_len;
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request->data += transfer_len;
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/* Total length shall not become negative */
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/* Total length shall not become negative */
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if (request->size < 0) {
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if (request->data_left < 0) {
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USB_MSG("Invalid amount of data received");
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USB_MSG("Invalid amount of data received");
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return EXIT_FAILURE;
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return EXIT_FAILURE;
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}
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}
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#ifdef DEBUG
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} while (0 != request->data_left);
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/* TODO: REMOVEME (dumping of data transfer) */
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{
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int i;
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USB_MSG("RECEIVED: %d", transfer_len);
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for (i = 0; i < transfer_len; i++)
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USB_MSG("0x%02X: %c",
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(request->data-transfer_len)[i],
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(request->data-transfer_len)[i]);
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}
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#endif
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} while (0 != request->size);
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} else if (0 == request->direction) {
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} else if (0 == request->direction) {
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do {
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do {
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temp_req = *request;
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temp_req = *request;
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/* Decide transfer size */
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/* Decide temporary transfer size */
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if (temp_req.size > (int)temp_req.max_packet_size) {
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if (temp_req.data_left > (int)temp_req.max_packet_size)
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temp_req.size = temp_req.max_packet_size;
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temp_req.data_left = temp_req.max_packet_size;
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}
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request->data += temp_req.size;
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/* Alter actual transfer size */
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request->size -= temp_req.size;
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request->data += temp_req.data_left;
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request->data_left -= temp_req.data_left;
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/* Total length shall not become negative */
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/* Total length shall not become negative */
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USB_ASSERT(request->size >= 0,
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USB_ASSERT(request->data_left >= 0,
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"Invalid amount of transfer data calculated");
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"Invalid amount of transfer data calculated");
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/* Start actual data transfer */
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/* Start actual data transfer */
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@ -858,7 +871,7 @@ hcd_data_transfer(hcd_device_state * this_device, hcd_datarequest * request)
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HCD_DIRECTION_OUT))
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HCD_DIRECTION_OUT))
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return EXIT_FAILURE;
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return EXIT_FAILURE;
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} while (0 != request->size);
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} while (0 != request->data_left);
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} else
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} else
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USB_ASSERT(0, "Invalid transfer direction");
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USB_ASSERT(0, "Invalid transfer direction");
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@ -23,7 +23,7 @@
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*===========================================================================*/
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*===========================================================================*/
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static int hcd_fill_configuration(hcd_reg1 *, int, hcd_configuration *, int);
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static int hcd_fill_configuration(hcd_reg1 *, int, hcd_configuration *, int);
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static int hcd_fill_interface(hcd_reg1 *, int, hcd_interface *, int);
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static int hcd_fill_interface(hcd_reg1 *, int, hcd_interface *, int);
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static int hcd_fill_endpoint(hcd_reg1 *, int, hcd_endpoint *, int);
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static int hcd_fill_endpoint(hcd_reg1 *, int, hcd_endpoint *);
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/*===========================================================================*
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/*===========================================================================*
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@ -343,10 +343,9 @@ hcd_buffer_to_tree(hcd_reg1 * buf, int len, hcd_configuration * c)
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if (NULL == i)
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if (NULL == i)
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goto PARSE_ERROR;
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goto PARSE_ERROR;
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e = &(i->endpoint[ep_num]);
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e = &(i->endpoint[ep_num++]);
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if (EXIT_SUCCESS != hcd_fill_endpoint(buf, len,
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if (EXIT_SUCCESS != hcd_fill_endpoint(buf, len, e))
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e, ep_num++))
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goto PARSE_ERROR;
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goto PARSE_ERROR;
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} else
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} else
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USB_DBG("Unhandled descriptor type 0x%02X",
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USB_DBG("Unhandled descriptor type 0x%02X",
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@ -507,6 +506,7 @@ hcd_fill_interface(hcd_reg1 * buf, int len, hcd_interface * i, int num)
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if (sizeof(*desc) != desc->bLength)
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if (sizeof(*desc) != desc->bLength)
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return EXIT_FAILURE;
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return EXIT_FAILURE;
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/* It is mandatory to supply interfaces in correct order */
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if (desc->bInterfaceNumber != num)
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if (desc->bInterfaceNumber != num)
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return EXIT_FAILURE;
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return EXIT_FAILURE;
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@ -541,7 +541,7 @@ hcd_fill_interface(hcd_reg1 * buf, int len, hcd_interface * i, int num)
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* hcd_fill_endpoint *
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* hcd_fill_endpoint *
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*===========================================================================*/
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*===========================================================================*/
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static int
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static int
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hcd_fill_endpoint(hcd_reg1 * buf, int len, hcd_endpoint * e, int num)
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hcd_fill_endpoint(hcd_reg1 * buf, int len, hcd_endpoint * e)
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{
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{
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hcd_endpoint_descriptor * desc;
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hcd_endpoint_descriptor * desc;
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@ -549,7 +549,7 @@ hcd_fill_endpoint(hcd_reg1 * buf, int len, hcd_endpoint * e, int num)
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desc = (hcd_endpoint_descriptor *)buf;
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desc = (hcd_endpoint_descriptor *)buf;
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USB_DBG("Endpoint #%d", num);
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USB_DBG("Endpoint #%d", UE_GET_ADDR(desc->bEndpointAddress));
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if (UDESC_ENDPOINT != desc->bDescriptorType)
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if (UDESC_ENDPOINT != desc->bDescriptorType)
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return EXIT_FAILURE;
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return EXIT_FAILURE;
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@ -631,7 +631,7 @@ musb_am335x_usbx_isr(void * data)
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static int
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static int
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musb_am335x_irqstat0_to_ep(int irqstat0)
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musb_am335x_irqstat0_to_ep(int irqstat0)
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{
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{
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int ep;
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hcd_reg1 ep;
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DEBUG_DUMP;
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DEBUG_DUMP;
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@ -640,16 +640,20 @@ musb_am335x_irqstat0_to_ep(int irqstat0)
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while (0 == (irqstat0 & 0x01)) {
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while (0 == (irqstat0 & 0x01)) {
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irqstat0 >>= 1;
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irqstat0 >>= 1;
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ep++;
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ep++;
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USB_ASSERT(ep < 32, "Invalid IRQSTAT0 supplied (1)");
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/* Must be within two consecutive EP sets */
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USB_ASSERT(ep < (2 * HCD_TOTAL_EP),
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||||||
|
"Invalid IRQSTAT0 supplied (1)");
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Convert RX interrupt to EP number */
|
/* Convert RX interrupt to EP number */
|
||||||
if (ep >= 16) {
|
if (ep >= HCD_TOTAL_EP) {
|
||||||
ep -= 16;
|
ep -= HCD_TOTAL_EP;
|
||||||
USB_ASSERT(ep != 0, "Invalid IRQSTAT0 supplied (2)");
|
/* Must not be control EP */
|
||||||
|
USB_ASSERT(ep != HCD_DEFAULT_EP,
|
||||||
|
"Invalid IRQSTAT0 supplied (2)");
|
||||||
}
|
}
|
||||||
|
|
||||||
return ep;
|
return (int)ep;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
|
@ -16,13 +16,13 @@
|
||||||
* Local prototypes *
|
* Local prototypes *
|
||||||
*===========================================================================*/
|
*===========================================================================*/
|
||||||
static void musb_set_state(musb_core_config *);
|
static void musb_set_state(musb_core_config *);
|
||||||
static int musb_check_rxpktrdy(void *, int);
|
static int musb_check_rxpktrdy(void *, hcd_reg1);
|
||||||
static void musb_in_stage_cleanup(void *, int);
|
static void musb_in_stage_cleanup(void *, hcd_reg1);
|
||||||
static void musb_clear_rxpktrdy(void *, int);
|
static void musb_clear_rxpktrdy(void *, hcd_reg1);
|
||||||
static void musb_clear_statuspkt(void *);
|
static void musb_clear_statuspkt(void *);
|
||||||
static int musb_get_count(void *);
|
static int musb_get_count(void *);
|
||||||
static void musb_read_fifo(void *, void *, int, int);
|
static void musb_read_fifo(void *, void *, int, hcd_reg1);
|
||||||
static void musb_write_fifo(void *, void *, int, int);
|
static void musb_write_fifo(void *, void *, int, hcd_reg1);
|
||||||
|
|
||||||
|
|
||||||
/*===========================================================================*
|
/*===========================================================================*
|
||||||
|
@ -43,8 +43,8 @@ musb_set_state(musb_core_config * cfg)
|
||||||
|
|
||||||
r = cfg->regs;
|
r = cfg->regs;
|
||||||
|
|
||||||
USB_ASSERT(cfg->ep <= 15, "Invalid EP supplied");
|
USB_ASSERT(cfg->ep <= HCD_LAST_EP, "Invalid EP supplied");
|
||||||
USB_ASSERT(cfg->addr <= 127, "Invalid device address supplied");
|
USB_ASSERT(cfg->addr <= HCD_LAST_ADDR, "Invalid address supplied");
|
||||||
|
|
||||||
/* Set EP and address to be used in next MUSB command */
|
/* Set EP and address to be used in next MUSB command */
|
||||||
|
|
||||||
|
@ -62,7 +62,7 @@ musb_set_state(musb_core_config * cfg)
|
||||||
* musb_check_rxpktrdy *
|
* musb_check_rxpktrdy *
|
||||||
*===========================================================================*/
|
*===========================================================================*/
|
||||||
static int
|
static int
|
||||||
musb_check_rxpktrdy(void * cfg, int ep_num)
|
musb_check_rxpktrdy(void * cfg, hcd_reg1 ep_num)
|
||||||
{
|
{
|
||||||
void * r;
|
void * r;
|
||||||
|
|
||||||
|
@ -74,7 +74,7 @@ musb_check_rxpktrdy(void * cfg, int ep_num)
|
||||||
musb_set_state((musb_core_config *)cfg);
|
musb_set_state((musb_core_config *)cfg);
|
||||||
|
|
||||||
/* Check for RXPKTRDY */
|
/* Check for RXPKTRDY */
|
||||||
if (0 == ep_num) {
|
if (HCD_DEFAULT_EP == ep_num) {
|
||||||
/* Get control status register for EP 0 */
|
/* Get control status register for EP 0 */
|
||||||
if (HCD_RD2(r, MUSB_REG_HOST_CSR0) &
|
if (HCD_RD2(r, MUSB_REG_HOST_CSR0) &
|
||||||
MUSB_VAL_HOST_CSR0_RXPKTRDY)
|
MUSB_VAL_HOST_CSR0_RXPKTRDY)
|
||||||
|
@ -94,14 +94,14 @@ musb_check_rxpktrdy(void * cfg, int ep_num)
|
||||||
* musb_in_stage_cleanup *
|
* musb_in_stage_cleanup *
|
||||||
*===========================================================================*/
|
*===========================================================================*/
|
||||||
static void
|
static void
|
||||||
musb_in_stage_cleanup(void * cfg, int ep_num)
|
musb_in_stage_cleanup(void * cfg, hcd_reg1 ep_num)
|
||||||
{
|
{
|
||||||
DEBUG_DUMP;
|
DEBUG_DUMP;
|
||||||
|
|
||||||
musb_clear_rxpktrdy(cfg, ep_num);
|
musb_clear_rxpktrdy(cfg, ep_num);
|
||||||
|
|
||||||
/* For control EP 0 also clear STATUSPKT */
|
/* For control EP 0 also clear STATUSPKT */
|
||||||
if (0 == ep_num)
|
if (HCD_DEFAULT_EP == ep_num)
|
||||||
musb_clear_statuspkt(cfg);
|
musb_clear_statuspkt(cfg);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -110,7 +110,7 @@ musb_in_stage_cleanup(void * cfg, int ep_num)
|
||||||
* musb_clear_rxpktrdy *
|
* musb_clear_rxpktrdy *
|
||||||
*===========================================================================*/
|
*===========================================================================*/
|
||||||
static void
|
static void
|
||||||
musb_clear_rxpktrdy(void * cfg, int ep_num)
|
musb_clear_rxpktrdy(void * cfg, hcd_reg1 ep_num)
|
||||||
{
|
{
|
||||||
void * r;
|
void * r;
|
||||||
hcd_reg2 host_csr;
|
hcd_reg2 host_csr;
|
||||||
|
@ -123,7 +123,7 @@ musb_clear_rxpktrdy(void * cfg, int ep_num)
|
||||||
musb_set_state((musb_core_config *)cfg);
|
musb_set_state((musb_core_config *)cfg);
|
||||||
|
|
||||||
/* Check for RXPKTRDY */
|
/* Check for RXPKTRDY */
|
||||||
if (0 == ep_num) {
|
if (HCD_DEFAULT_EP == ep_num) {
|
||||||
/* Get control status register for EP 0 */
|
/* Get control status register for EP 0 */
|
||||||
host_csr = HCD_RD2(r, MUSB_REG_HOST_CSR0);
|
host_csr = HCD_RD2(r, MUSB_REG_HOST_CSR0);
|
||||||
|
|
||||||
|
@ -191,7 +191,7 @@ musb_get_count(void * cfg)
|
||||||
* musb_read_fifo *
|
* musb_read_fifo *
|
||||||
*===========================================================================*/
|
*===========================================================================*/
|
||||||
static void
|
static void
|
||||||
musb_read_fifo(void * cfg, void * output, int size, int fifo_num)
|
musb_read_fifo(void * cfg, void * output, int size, hcd_reg1 fifo_num)
|
||||||
{
|
{
|
||||||
void * r;
|
void * r;
|
||||||
|
|
||||||
|
@ -202,7 +202,7 @@ musb_read_fifo(void * cfg, void * output, int size, int fifo_num)
|
||||||
|
|
||||||
DEBUG_DUMP;
|
DEBUG_DUMP;
|
||||||
|
|
||||||
USB_ASSERT((fifo_num >= 0) && (fifo_num <= 15), "Wrong FIFO number");
|
USB_ASSERT(fifo_num <= HCD_LAST_EP, "Invalid FIFO number");
|
||||||
|
|
||||||
r = ((musb_core_config *)cfg)->regs;
|
r = ((musb_core_config *)cfg)->regs;
|
||||||
fifo_addr = MUSB_REG_FIFO0 + (fifo_num * MUSB_REG_FIFO_LEN);
|
fifo_addr = MUSB_REG_FIFO0 + (fifo_num * MUSB_REG_FIFO_LEN);
|
||||||
|
@ -216,7 +216,7 @@ musb_read_fifo(void * cfg, void * output, int size, int fifo_num)
|
||||||
output_w = (hcd_reg4 *)output;
|
output_w = (hcd_reg4 *)output;
|
||||||
|
|
||||||
/* Try and copy aligned words */
|
/* Try and copy aligned words */
|
||||||
if (0 == ((hcd_addr)output_w % 4)) {
|
if (0 == ((hcd_addr)output_w % sizeof(hcd_addr))) {
|
||||||
|
|
||||||
while (size > (int)(sizeof(*output_w) - 1)) {
|
while (size > (int)(sizeof(*output_w) - 1)) {
|
||||||
*output_w++ = HCD_RD4(r, fifo_addr);
|
*output_w++ = HCD_RD4(r, fifo_addr);
|
||||||
|
@ -238,7 +238,7 @@ musb_read_fifo(void * cfg, void * output, int size, int fifo_num)
|
||||||
* musb_write_fifo *
|
* musb_write_fifo *
|
||||||
*===========================================================================*/
|
*===========================================================================*/
|
||||||
static void
|
static void
|
||||||
musb_write_fifo(void * cfg, void * input, int size, int fifo_num)
|
musb_write_fifo(void * cfg, void * input, int size, hcd_reg1 fifo_num)
|
||||||
{
|
{
|
||||||
void * r;
|
void * r;
|
||||||
|
|
||||||
|
@ -249,7 +249,7 @@ musb_write_fifo(void * cfg, void * input, int size, int fifo_num)
|
||||||
|
|
||||||
DEBUG_DUMP;
|
DEBUG_DUMP;
|
||||||
|
|
||||||
USB_ASSERT((fifo_num >= 0) && (fifo_num <= 15), "Wrong FIFO number");
|
USB_ASSERT(fifo_num <= HCD_LAST_EP, "Invalid FIFO number");
|
||||||
|
|
||||||
r = ((musb_core_config *)cfg)->regs;
|
r = ((musb_core_config *)cfg)->regs;
|
||||||
fifo_addr = MUSB_REG_FIFO0 + (fifo_num * MUSB_REG_FIFO_LEN);
|
fifo_addr = MUSB_REG_FIFO0 + (fifo_num * MUSB_REG_FIFO_LEN);
|
||||||
|
@ -263,7 +263,7 @@ musb_write_fifo(void * cfg, void * input, int size, int fifo_num)
|
||||||
input_w = (hcd_reg4 *)input;
|
input_w = (hcd_reg4 *)input;
|
||||||
|
|
||||||
/* Try and copy aligned words */
|
/* Try and copy aligned words */
|
||||||
if (0 == ((hcd_addr)input_w % 4)) {
|
if (0 == ((hcd_addr)input_w % sizeof(hcd_addr))) {
|
||||||
|
|
||||||
while (size > (int)(sizeof(*input_w) - 1)) {
|
while (size > (int)(sizeof(*input_w) - 1)) {
|
||||||
HCD_WR4(r, fifo_addr, *input_w++);
|
HCD_WR4(r, fifo_addr, *input_w++);
|
||||||
|
@ -461,9 +461,6 @@ void
|
||||||
musb_rx_stage(void * cfg, hcd_datarequest * request)
|
musb_rx_stage(void * cfg, hcd_datarequest * request)
|
||||||
{
|
{
|
||||||
musb_core_config * core;
|
musb_core_config * core;
|
||||||
#if 0
|
|
||||||
hcd_reg2 intrrxe;
|
|
||||||
#endif
|
|
||||||
hcd_reg2 host_rxcsr;
|
hcd_reg2 host_rxcsr;
|
||||||
hcd_reg1 host_rxtype;
|
hcd_reg1 host_rxtype;
|
||||||
void * r;
|
void * r;
|
||||||
|
@ -475,7 +472,7 @@ musb_rx_stage(void * cfg, hcd_datarequest * request)
|
||||||
|
|
||||||
USB_ASSERT(request->max_packet_size <= 1024,
|
USB_ASSERT(request->max_packet_size <= 1024,
|
||||||
"Invalid wMaxPacketSize");
|
"Invalid wMaxPacketSize");
|
||||||
USB_ASSERT((core->ep <= 15) && (core->ep > 0),
|
USB_ASSERT((core->ep <= HCD_LAST_EP) && (core->ep > HCD_DEFAULT_EP),
|
||||||
"Invalid bulk EP supplied");
|
"Invalid bulk EP supplied");
|
||||||
|
|
||||||
/* Set EP and device address to be used in this command */
|
/* Set EP and device address to be used in this command */
|
||||||
|
@ -513,12 +510,17 @@ musb_rx_stage(void * cfg, hcd_datarequest * request)
|
||||||
else if (HCD_TRANSFER_INTERRUPT == request->type)
|
else if (HCD_TRANSFER_INTERRUPT == request->type)
|
||||||
HCD_WR1(r, MUSB_REG_HOST_RXINTERVAL, request->interval);
|
HCD_WR1(r, MUSB_REG_HOST_RXINTERVAL, request->interval);
|
||||||
|
|
||||||
/* Not required in some MUSB implementations */
|
|
||||||
#if 0
|
#if 0
|
||||||
|
{
|
||||||
|
/* Not required by all MUSB implementations, but
|
||||||
|
* left here just in case */
|
||||||
|
hcd_reg2 intrrxe;
|
||||||
|
|
||||||
/* Enable this interrupt */
|
/* Enable this interrupt */
|
||||||
intrrxe = HCD_RD2(r, MUSB_REG_INTRRXE);
|
intrrxe = HCD_RD2(r, MUSB_REG_INTRRXE);
|
||||||
HCD_SET(intrrxe, HCD_BIT(core->ep));
|
HCD_SET(intrrxe, HCD_BIT(core->ep));
|
||||||
HCD_WR2(r, MUSB_REG_INTRRXE, intrrxe);
|
HCD_WR2(r, MUSB_REG_INTRRXE, intrrxe);
|
||||||
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/* TODO: One reusable FIFO, no double buffering */
|
/* TODO: One reusable FIFO, no double buffering */
|
||||||
|
@ -529,21 +531,15 @@ musb_rx_stage(void * cfg, hcd_datarequest * request)
|
||||||
HCD_WR2(r, MUSB_REG_RXFIFOADDR, MUSB_VAL_XXFIFOADDR_EP0_END);
|
HCD_WR2(r, MUSB_REG_RXFIFOADDR, MUSB_VAL_XXFIFOADDR_EP0_END);
|
||||||
HCD_WR1(r, MUSB_REG_RXFIFOSZ, MUSB_VAL_XXFIFOSZ_4096);
|
HCD_WR1(r, MUSB_REG_RXFIFOSZ, MUSB_VAL_XXFIFOSZ_4096);
|
||||||
|
|
||||||
/* TODO: decide which is better (or working at all when we use more
|
|
||||||
* than one transfer for bulk data in single device) */
|
|
||||||
#if 0
|
|
||||||
/* Make controller reconfigure */
|
/* Make controller reconfigure */
|
||||||
host_rxcsr = HCD_RD2(r, MUSB_REG_HOST_RXCSR);
|
host_rxcsr = HCD_RD2(r, MUSB_REG_HOST_RXCSR);
|
||||||
|
if (MUSB_DATATOG_UNKNOWN == core->datatog_rx[core->ep]) {
|
||||||
|
/* Reset DATA toggle on first transfer */
|
||||||
HCD_SET(host_rxcsr, MUSB_VAL_HOST_RXCSR_CLRDATATOG);
|
HCD_SET(host_rxcsr, MUSB_VAL_HOST_RXCSR_CLRDATATOG);
|
||||||
|
core->datatog_rx[core->ep] = MUSB_DATATOG_INIT;
|
||||||
|
}
|
||||||
HCD_SET(host_rxcsr, MUSB_VAL_HOST_RXCSR_FLUSHFIFO);
|
HCD_SET(host_rxcsr, MUSB_VAL_HOST_RXCSR_FLUSHFIFO);
|
||||||
HCD_WR2(r, MUSB_REG_HOST_RXCSR, host_rxcsr);
|
HCD_WR2(r, MUSB_REG_HOST_RXCSR, host_rxcsr);
|
||||||
#else
|
|
||||||
/* Reset and flush */
|
|
||||||
host_rxcsr = 0;
|
|
||||||
HCD_SET(host_rxcsr, MUSB_VAL_HOST_RXCSR_CLRDATATOG);
|
|
||||||
HCD_SET(host_rxcsr, MUSB_VAL_HOST_RXCSR_FLUSHFIFO);
|
|
||||||
HCD_WR2(r, MUSB_REG_HOST_RXCSR, host_rxcsr);
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Request packet */
|
/* Request packet */
|
||||||
host_rxcsr = HCD_RD2(r, MUSB_REG_HOST_RXCSR);
|
host_rxcsr = HCD_RD2(r, MUSB_REG_HOST_RXCSR);
|
||||||
|
@ -559,9 +555,6 @@ void
|
||||||
musb_tx_stage(void * cfg, hcd_datarequest * request)
|
musb_tx_stage(void * cfg, hcd_datarequest * request)
|
||||||
{
|
{
|
||||||
musb_core_config * core;
|
musb_core_config * core;
|
||||||
#if 0
|
|
||||||
hcd_reg2 intrtxe;
|
|
||||||
#endif
|
|
||||||
hcd_reg2 host_txcsr;
|
hcd_reg2 host_txcsr;
|
||||||
hcd_reg1 host_txtype;
|
hcd_reg1 host_txtype;
|
||||||
void * r;
|
void * r;
|
||||||
|
@ -573,7 +566,7 @@ musb_tx_stage(void * cfg, hcd_datarequest * request)
|
||||||
|
|
||||||
USB_ASSERT(request->max_packet_size <= 1024,
|
USB_ASSERT(request->max_packet_size <= 1024,
|
||||||
"Invalid wMaxPacketSize");
|
"Invalid wMaxPacketSize");
|
||||||
USB_ASSERT((core->ep <= 15) && (core->ep > 0),
|
USB_ASSERT((core->ep <= HCD_LAST_EP) && (core->ep > HCD_DEFAULT_EP),
|
||||||
"Invalid bulk EP supplied");
|
"Invalid bulk EP supplied");
|
||||||
|
|
||||||
/* Set EP and device address to be used in this command */
|
/* Set EP and device address to be used in this command */
|
||||||
|
@ -611,12 +604,17 @@ musb_tx_stage(void * cfg, hcd_datarequest * request)
|
||||||
else if (HCD_TRANSFER_INTERRUPT == request->type)
|
else if (HCD_TRANSFER_INTERRUPT == request->type)
|
||||||
HCD_WR1(r, MUSB_REG_HOST_TXINTERVAL, request->interval);
|
HCD_WR1(r, MUSB_REG_HOST_TXINTERVAL, request->interval);
|
||||||
|
|
||||||
/* Not required in some MUSB implementations */
|
|
||||||
#if 0
|
#if 0
|
||||||
|
{
|
||||||
|
/* Not required by all MUSB implementations, but
|
||||||
|
* left here just in case */
|
||||||
|
hcd_reg2 intrtxe;
|
||||||
|
|
||||||
/* Enable this interrupt */
|
/* Enable this interrupt */
|
||||||
intrtxe = HCD_RD2(r, MUSB_REG_INTRTXE);
|
intrtxe = HCD_RD2(r, MUSB_REG_INTRTXE);
|
||||||
HCD_SET(intrtxe, HCD_BIT(core->ep));
|
HCD_SET(intrtxe, HCD_BIT(core->ep));
|
||||||
HCD_WR2(r, MUSB_REG_INTRTXE, intrtxe);
|
HCD_WR2(r, MUSB_REG_INTRTXE, intrtxe);
|
||||||
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/* TODO: One reusable FIFO, no double buffering */
|
/* TODO: One reusable FIFO, no double buffering */
|
||||||
|
@ -627,9 +625,6 @@ musb_tx_stage(void * cfg, hcd_datarequest * request)
|
||||||
HCD_WR2(r, MUSB_REG_TXFIFOADDR, MUSB_VAL_XXFIFOADDR_EP0_END);
|
HCD_WR2(r, MUSB_REG_TXFIFOADDR, MUSB_VAL_XXFIFOADDR_EP0_END);
|
||||||
HCD_WR1(r, MUSB_REG_TXFIFOSZ, MUSB_VAL_XXFIFOSZ_4096);
|
HCD_WR1(r, MUSB_REG_TXFIFOSZ, MUSB_VAL_XXFIFOSZ_4096);
|
||||||
|
|
||||||
/* TODO: decide which is better (or working at all when we use more
|
|
||||||
* than one transfer for bulk data in single device) */
|
|
||||||
#if 0
|
|
||||||
/* Make controller reconfigure */
|
/* Make controller reconfigure */
|
||||||
host_txcsr = HCD_RD2(r, MUSB_REG_HOST_TXCSR);
|
host_txcsr = HCD_RD2(r, MUSB_REG_HOST_TXCSR);
|
||||||
HCD_CLR(host_txcsr, MUSB_VAL_HOST_TXCSR_DMAMODE);
|
HCD_CLR(host_txcsr, MUSB_VAL_HOST_TXCSR_DMAMODE);
|
||||||
|
@ -638,20 +633,16 @@ musb_tx_stage(void * cfg, hcd_datarequest * request)
|
||||||
HCD_SET(host_txcsr, MUSB_VAL_HOST_TXCSR_MODE);
|
HCD_SET(host_txcsr, MUSB_VAL_HOST_TXCSR_MODE);
|
||||||
HCD_CLR(host_txcsr, MUSB_VAL_HOST_TXCSR_ISO);
|
HCD_CLR(host_txcsr, MUSB_VAL_HOST_TXCSR_ISO);
|
||||||
HCD_CLR(host_txcsr, MUSB_VAL_HOST_TXCSR_AUTOSET);
|
HCD_CLR(host_txcsr, MUSB_VAL_HOST_TXCSR_AUTOSET);
|
||||||
|
if (MUSB_DATATOG_UNKNOWN == core->datatog_tx[core->ep]) {
|
||||||
|
/* Reset DATA toggle on first transfer */
|
||||||
HCD_SET(host_txcsr, MUSB_VAL_HOST_TXCSR_CLRDATATOG);
|
HCD_SET(host_txcsr, MUSB_VAL_HOST_TXCSR_CLRDATATOG);
|
||||||
|
core->datatog_tx[core->ep] = MUSB_DATATOG_INIT;
|
||||||
|
}
|
||||||
HCD_SET(host_txcsr, MUSB_VAL_HOST_TXCSR_FLUSHFIFO);
|
HCD_SET(host_txcsr, MUSB_VAL_HOST_TXCSR_FLUSHFIFO);
|
||||||
HCD_WR2(r, MUSB_REG_HOST_TXCSR, host_txcsr);
|
HCD_WR2(r, MUSB_REG_HOST_TXCSR, host_txcsr);
|
||||||
#else
|
|
||||||
/* Reset and flush */
|
|
||||||
host_txcsr = 0;
|
|
||||||
HCD_SET(host_txcsr, MUSB_VAL_HOST_TXCSR_MODE);
|
|
||||||
HCD_SET(host_txcsr, MUSB_VAL_HOST_TXCSR_CLRDATATOG);
|
|
||||||
HCD_SET(host_txcsr, MUSB_VAL_HOST_TXCSR_FLUSHFIFO);
|
|
||||||
HCD_WR2(r, MUSB_REG_HOST_TXCSR, host_txcsr);
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Put data in FIFO */
|
/* Put data in FIFO */
|
||||||
musb_write_fifo(cfg, request->data, request->size, core->ep);
|
musb_write_fifo(cfg, request->data, request->data_left, core->ep);
|
||||||
|
|
||||||
/* Request packet */
|
/* Request packet */
|
||||||
host_txcsr = HCD_RD2(r, MUSB_REG_HOST_TXCSR);
|
host_txcsr = HCD_RD2(r, MUSB_REG_HOST_TXCSR);
|
||||||
|
@ -760,7 +751,7 @@ musb_out_status_stage(void * cfg)
|
||||||
* musb_read_data *
|
* musb_read_data *
|
||||||
*===========================================================================*/
|
*===========================================================================*/
|
||||||
int
|
int
|
||||||
musb_read_data(void * cfg, hcd_reg1 * buffer, int ep_num)
|
musb_read_data(void * cfg, hcd_reg1 * buffer, hcd_reg1 ep_num)
|
||||||
{
|
{
|
||||||
int count;
|
int count;
|
||||||
|
|
||||||
|
|
|
@ -11,6 +11,15 @@
|
||||||
/*===========================================================================*
|
/*===========================================================================*
|
||||||
* Types and constants *
|
* Types and constants *
|
||||||
*===========================================================================*/
|
*===========================================================================*/
|
||||||
|
/* Holds info on DATA toggle (DATA0/DATA1) initialization,
|
||||||
|
* required by bulk transfers */
|
||||||
|
typedef enum {
|
||||||
|
|
||||||
|
MUSB_DATATOG_UNKNOWN = 0, /* Default with memset 0 */
|
||||||
|
MUSB_DATATOG_INIT
|
||||||
|
}
|
||||||
|
musb_datatog;
|
||||||
|
|
||||||
/* Structure to hold Mentor USB core configuration
|
/* Structure to hold Mentor USB core configuration
|
||||||
* May be more than one on a single chip
|
* May be more than one on a single chip
|
||||||
* Should be initialized by MUSB's variant specific code (like AM335x) */
|
* Should be initialized by MUSB's variant specific code (like AM335x) */
|
||||||
|
@ -19,6 +28,8 @@ typedef struct {
|
||||||
void * regs; /* Points to beginning of memory mapped registers */
|
void * regs; /* Points to beginning of memory mapped registers */
|
||||||
hcd_reg1 ep; /* Currently used endpoint */
|
hcd_reg1 ep; /* Currently used endpoint */
|
||||||
hcd_reg1 addr; /* Currently used address */
|
hcd_reg1 addr; /* Currently used address */
|
||||||
|
musb_datatog datatog_tx[HCD_TOTAL_EP];
|
||||||
|
musb_datatog datatog_rx[HCD_TOTAL_EP];
|
||||||
}
|
}
|
||||||
musb_core_config;
|
musb_core_config;
|
||||||
|
|
||||||
|
@ -41,7 +52,7 @@ void musb_in_data_stage(void *);
|
||||||
void musb_out_data_stage(void *);
|
void musb_out_data_stage(void *);
|
||||||
void musb_in_status_stage(void *);
|
void musb_in_status_stage(void *);
|
||||||
void musb_out_status_stage(void *);
|
void musb_out_status_stage(void *);
|
||||||
int musb_read_data(void *, hcd_reg1 *, int);
|
int musb_read_data(void *, hcd_reg1 *, hcd_reg1);
|
||||||
int musb_check_error(void *, hcd_transfer, hcd_direction);
|
int musb_check_error(void *, hcd_transfer, hcd_direction);
|
||||||
|
|
||||||
|
|
||||||
|
|
|
@ -194,7 +194,7 @@ hcd_event;
|
||||||
struct hcd_datarequest {
|
struct hcd_datarequest {
|
||||||
|
|
||||||
char * data;
|
char * data;
|
||||||
int size;
|
int data_left;
|
||||||
int endpoint;
|
int endpoint;
|
||||||
int direction;
|
int direction;
|
||||||
unsigned int max_packet_size;
|
unsigned int max_packet_size;
|
||||||
|
@ -218,9 +218,12 @@ typedef struct hcd_datarequest hcd_datarequest;
|
||||||
#define HCD_NANOSLEEP_USEC(usec) ((usec) * HCD_MILI)
|
#define HCD_NANOSLEEP_USEC(usec) ((usec) * HCD_MILI)
|
||||||
|
|
||||||
/* Default USB communication parameters */
|
/* Default USB communication parameters */
|
||||||
#define HCD_DEFAULT_EP 0x00
|
#define HCD_DEFAULT_EP 0x00u
|
||||||
#define HCD_DEFAULT_ADDR 0x00
|
#define HCD_DEFAULT_ADDR 0x00u
|
||||||
#define HCD_DEFAULT_CONFIG 0x00
|
#define HCD_DEFAULT_CONFIG 0x00u
|
||||||
|
#define HCD_LAST_ADDR 0x7Fu
|
||||||
|
#define HCD_LAST_EP 0x0Fu
|
||||||
|
#define HCD_TOTAL_EP 0x10u
|
||||||
|
|
||||||
/* TODO: One device only */
|
/* TODO: One device only */
|
||||||
#define HCD_ATTACHED_ADDR 0x01
|
#define HCD_ATTACHED_ADDR 0x01
|
||||||
|
@ -228,6 +231,10 @@ typedef struct hcd_datarequest hcd_datarequest;
|
||||||
/* Translates configuration number for 'set configuration' */
|
/* Translates configuration number for 'set configuration' */
|
||||||
#define HCD_SET_CONFIG_NUM(num) ((num)+0x01u)
|
#define HCD_SET_CONFIG_NUM(num) ((num)+0x01u)
|
||||||
|
|
||||||
|
/* Default MaxPacketSize for control transfer */
|
||||||
|
#define HCD_LS_MAXPACKETSIZE 8u
|
||||||
|
#define HCD_HS_MAXPACKETSIZE 64u
|
||||||
|
|
||||||
|
|
||||||
/*===========================================================================*
|
/*===========================================================================*
|
||||||
* Operating system specific *
|
* Operating system specific *
|
||||||
|
|
|
@ -32,7 +32,7 @@ struct hcd_driver_state {
|
||||||
void (*out_data_stage) (void *);
|
void (*out_data_stage) (void *);
|
||||||
void (*in_status_stage) (void *);
|
void (*in_status_stage) (void *);
|
||||||
void (*out_status_stage) (void *);
|
void (*out_status_stage) (void *);
|
||||||
int (*read_data) (void *, hcd_reg1 *, int);
|
int (*read_data) (void *, hcd_reg1 *, hcd_reg1);
|
||||||
int (*check_error) (void *, hcd_transfer, hcd_direction);
|
int (*check_error) (void *, hcd_transfer, hcd_direction);
|
||||||
|
|
||||||
/* Controller's private data (like mapped registers) */
|
/* Controller's private data (like mapped registers) */
|
||||||
|
|
|
@ -11,8 +11,8 @@
|
||||||
/* Current printf implementation for dumping important messages */
|
/* Current printf implementation for dumping important messages */
|
||||||
#include <stdio.h>
|
#include <stdio.h>
|
||||||
|
|
||||||
#if 1
|
/* In case of verbose debug output, enable this: */
|
||||||
/* TODO: should be elsewhere */
|
#if 0
|
||||||
#define DEBUG
|
#define DEBUG
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
@ -45,8 +45,8 @@
|
||||||
} while(0)
|
} while(0)
|
||||||
|
|
||||||
#else
|
#else
|
||||||
#define DEBUG_DUMP
|
#define DEBUG_DUMP ((void)0)
|
||||||
#define USB_DBG(fmt, ...)
|
#define USB_DBG(fmt, ...) ((void)0)
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
@ -56,7 +56,8 @@
|
||||||
#define USB_ASSERT(cond, otherwise) \
|
#define USB_ASSERT(cond, otherwise) \
|
||||||
do { \
|
do { \
|
||||||
if(!(cond)) { \
|
if(!(cond)) { \
|
||||||
USB_MSG("ERROR - "otherwise); \
|
USB_MSG("ASSERTION ERROR (%s:%d) - " \
|
||||||
|
otherwise, __func__, __LINE__); \
|
||||||
exit(EXIT_FAILURE); \
|
exit(EXIT_FAILURE); \
|
||||||
} \
|
} \
|
||||||
} while(0)
|
} while(0)
|
||||||
|
|
Loading…
Reference in a new issue