Functions that check arguments and return a status code and functions that
don't.
This commit is contained in:
Philip Homburg
parent
fecd153c2c
commit
e3d4c74393
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@ -8,7 +8,6 @@ Created: Jan 2000 by Philip Homburg <philip@cs.vu.nl>
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*/
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#include "../drivers.h"
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#define NDEBUG /* disable assertions */
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#include <assert.h>
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#include <ibm/pci.h>
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#include <sys/vm.h>
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@ -125,6 +124,10 @@ FORWARD _PROTOTYPE( char *pci_baseclass_name, (U8_t baseclass) );
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FORWARD _PROTOTYPE( char *pci_subclass_name, (U8_t baseclass,
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U8_t subclass, U8_t infclass) );
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FORWARD _PROTOTYPE( void ntostr, (unsigned n, char **str, char *end) );
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FORWARD _PROTOTYPE( u8_t pci_attr_r8_u, (int devind, int port) );
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FORWARD _PROTOTYPE( u32_t pci_attr_r32_u, (int devind, int port) );
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FORWARD _PROTOTYPE( u16_t pci_attr_rsts, (int devind) );
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FORWARD _PROTOTYPE( void pci_attr_wsts, (int devind, U16_t value) );
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FORWARD _PROTOTYPE( u16_t pcibr_std_rsts, (int busind) );
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@ -148,6 +151,7 @@ FORWARD _PROTOTYPE( u16_t pcii_rsts, (int busind) );
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FORWARD _PROTOTYPE( void pcii_wsts, (int busind, U16_t value) );
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FORWARD _PROTOTYPE( void print_capabilities, (int devind) );
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FORWARD _PROTOTYPE( int visible, (struct rs_pci *aclp, int devind) );
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FORWARD _PROTOTYPE( void print_hyper_cap, (int devind, U8_t capptr) );
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/*===========================================================================*
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* helper functions for I/O *
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@ -310,7 +314,7 @@ u16_t *didp;
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}
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/*===========================================================================*
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* pci_reserve3 *
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* pci_reserve2 *
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*===========================================================================*/
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PUBLIC int pci_reserve2(devind, proc)
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int devind;
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@ -321,7 +325,11 @@ int proc;
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struct io_range ior;
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struct mem_range mr;
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assert(devind <= nr_pcidev);
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if (devind < 0 || devind >= nr_pcidev)
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{
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printf("pci:pci_reserve2: bad devind: %d\n", devind);
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return EINVAL;
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}
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if(pcidev[devind].pd_inuse)
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return EBUSY;
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pcidev[devind].pd_inuse= 1;
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@ -405,16 +413,19 @@ endpoint_t proc;
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}
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/*===========================================================================*
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* pci_ids *
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* pci_ids_s *
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*===========================================================================*/
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PUBLIC void pci_ids(devind, vidp, didp)
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PUBLIC int pci_ids_s(devind, vidp, didp)
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int devind;
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u16_t *vidp;
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u16_t *didp;
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{
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assert(devind <= nr_pcidev);
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if (devind < 0 || devind >= nr_pcidev)
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return EINVAL;
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*vidp= pcidev[devind].pd_vid;
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*didp= pcidev[devind].pd_did;
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return OK;
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}
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/*===========================================================================*
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@ -436,15 +447,19 @@ u8_t busnr;
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}
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/*===========================================================================*
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* pci_slot_name *
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* pci_slot_name_s *
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*===========================================================================*/
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PUBLIC char *pci_slot_name(devind)
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PUBLIC int pci_slot_name_s(devind, cpp)
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int devind;
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char **cpp;
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{
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static char label[]= "ddd.ddd.ddd";
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char *end;
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char *p;
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if (devind < 0 || devind >= nr_pcidev)
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return EINVAL;
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p= label;
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end= label+sizeof(label);
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@ -456,7 +471,8 @@ int devind;
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ntostr(pcidev[devind].pd_func, &p, end);
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return label;
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*cpp= label;
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return OK;
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}
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/*===========================================================================*
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@ -480,9 +496,26 @@ u16_t did;
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}
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/*===========================================================================*
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* pci_attr_r8 *
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* pci_attr_r8_s *
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*===========================================================================*/
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PUBLIC u8_t pci_attr_r8(devind, port)
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PUBLIC int pci_attr_r8_s(devind, port, vp)
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int devind;
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int port;
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u8_t *vp;
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{
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if (devind < 0 || devind >= nr_pcidev)
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return EINVAL;
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if (port < 0 || port > 255)
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return EINVAL;
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*vp= pci_attr_r8_u(devind, port);
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return OK;
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}
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/*===========================================================================*
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* pci_attr_r8_u *
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*===========================================================================*/
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PRIVATE u8_t pci_attr_r8_u(devind, port)
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int devind;
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int port;
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{
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@ -508,9 +541,26 @@ int port;
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}
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/*===========================================================================*
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* pci_attr_r32 *
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* pci_attr_r32_s *
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*===========================================================================*/
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PUBLIC u32_t pci_attr_r32(devind, port)
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PUBLIC int pci_attr_r32_s(devind, port, vp)
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int devind;
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int port;
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u32_t *vp;
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{
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if (devind < 0 || devind >= nr_pcidev)
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return EINVAL;
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if (port < 0 || port > 256-4)
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return EINVAL;
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*vp= pci_attr_r32_u(devind, port);
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return OK;
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}
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/*===========================================================================*
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* pci_attr_r32_u *
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*===========================================================================*/
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PRIVATE u32_t pci_attr_r32_u(devind, port)
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int devind;
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int port;
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{
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@ -704,7 +754,7 @@ printf("probe_bus(%d)\n", busind);
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PSR_SSE|PSR_RMAS|PSR_RTAS);
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vid= pci_attr_r16(devind, PCI_VID);
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did= pci_attr_r16(devind, PCI_DID);
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headt= pci_attr_r8(devind, PCI_HEADT);
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headt= pci_attr_r8_u(devind, PCI_HEADT);
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sts= pci_attr_rsts(devind);
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#if 0
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@ -767,9 +817,9 @@ printf("probe_bus(%d)\n", busind);
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pci_attr_r16(devind, PCI_SUBDID));
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}
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baseclass= pci_attr_r8(devind, PCI_BCR);
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subclass= pci_attr_r8(devind, PCI_SCR);
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infclass= pci_attr_r8(devind, PCI_PIFR);
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baseclass= pci_attr_r8_u(devind, PCI_BCR);
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subclass= pci_attr_r8_u(devind, PCI_SCR);
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infclass= pci_attr_r8_u(devind, PCI_PIFR);
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s= pci_subclass_name(baseclass, subclass, infclass);
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if (!s)
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s= pci_baseclass_name(baseclass);
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@ -865,8 +915,8 @@ int devind;
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{
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int ilr, ipr, busnr, busind, cb_devind;
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ilr= pci_attr_r8(devind, PCI_ILR);
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ipr= pci_attr_r8(devind, PCI_IPR);
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ilr= pci_attr_r8_u(devind, PCI_ILR);
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ipr= pci_attr_r8_u(devind, PCI_IPR);
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if (ilr == 0)
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{
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static int first= 1;
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@ -1002,10 +1052,10 @@ int devind;
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record_bar(devind, 0);
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record_bar(devind, 1);
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base= ((pci_attr_r8(devind, PPB_IOBASE) & PPB_IOB_MASK) << 8) |
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base= ((pci_attr_r8_u(devind, PPB_IOBASE) & PPB_IOB_MASK) << 8) |
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(pci_attr_r16(devind, PPB_IOBASEU16) << 16);
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limit= 0xff |
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((pci_attr_r8(devind, PPB_IOLIMIT) & PPB_IOL_MASK) << 8) |
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((pci_attr_r8_u(devind, PPB_IOLIMIT) & PPB_IOL_MASK) << 8) |
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((~PPB_IOL_MASK & 0xff) << 8) |
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(pci_attr_r16(devind, PPB_IOLIMITU16) << 16);
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size= limit-base + 1;
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@ -1051,8 +1101,8 @@ int devind;
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record_bar(devind, 0);
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base= pci_attr_r32(devind, CBB_MEMBASE_0);
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limit= pci_attr_r32(devind, CBB_MEMLIMIT_0) |
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base= pci_attr_r32_u(devind, CBB_MEMBASE_0);
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limit= pci_attr_r32_u(devind, CBB_MEMLIMIT_0) |
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(~CBB_MEML_MASK & 0xffffffff);
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size= limit-base + 1;
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if (debug)
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@ -1061,8 +1111,8 @@ int devind;
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base, limit, size);
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}
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base= pci_attr_r32(devind, CBB_MEMBASE_1);
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limit= pci_attr_r32(devind, CBB_MEMLIMIT_1) |
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base= pci_attr_r32_u(devind, CBB_MEMBASE_1);
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limit= pci_attr_r32_u(devind, CBB_MEMLIMIT_1) |
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(~CBB_MEML_MASK & 0xffffffff);
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size= limit-base + 1;
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if (debug)
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@ -1071,8 +1121,8 @@ int devind;
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base, limit, size);
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}
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base= pci_attr_r32(devind, CBB_IOBASE_0);
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limit= pci_attr_r32(devind, CBB_IOLIMIT_0) |
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base= pci_attr_r32_u(devind, CBB_IOBASE_0);
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limit= pci_attr_r32_u(devind, CBB_IOLIMIT_0) |
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(~CBB_IOL_MASK & 0xffffffff);
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size= limit-base + 1;
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if (debug)
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@ -1081,8 +1131,8 @@ int devind;
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base, limit, size);
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}
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base= pci_attr_r32(devind, CBB_IOBASE_1);
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limit= pci_attr_r32(devind, CBB_IOLIMIT_1) |
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base= pci_attr_r32_u(devind, CBB_IOBASE_1);
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limit= pci_attr_r32_u(devind, CBB_IOLIMIT_1) |
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(~CBB_IOL_MASK & 0xffffffff);
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size= limit-base + 1;
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if (debug)
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@ -1104,12 +1154,12 @@ int bar_nr;
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reg= PCI_BAR+4*bar_nr;
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bar= pci_attr_r32(devind, reg);
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bar= pci_attr_r32_u(devind, reg);
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if (bar & PCI_BAR_IO)
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{
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/* Size register */
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pci_attr_w32(devind, reg, 0xffffffff);
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bar2= pci_attr_r32(devind, reg);
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bar2= pci_attr_r32_u(devind, reg);
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pci_attr_w32(devind, reg, bar);
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bar &= ~(u32_t)3; /* Clear non-address bits */
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@ -1122,7 +1172,6 @@ int bar_nr;
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}
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dev_bar_nr= pcidev[devind].pd_bar_nr++;
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assert(dev_bar_nr < BAR_NR);
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pcidev[devind].pd_bar[dev_bar_nr].pb_flags= PBF_IO;
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pcidev[devind].pd_bar[dev_bar_nr].pb_base= bar;
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pcidev[devind].pd_bar[dev_bar_nr].pb_size= bar2;
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@ -1137,7 +1186,7 @@ int bar_nr;
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{
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/* Size register */
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pci_attr_w32(devind, reg, 0xffffffff);
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bar2= pci_attr_r32(devind, reg);
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bar2= pci_attr_r32_u(devind, reg);
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pci_attr_w32(devind, reg, bar);
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if (bar2 == 0)
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@ -1158,7 +1207,6 @@ int bar_nr;
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}
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dev_bar_nr= pcidev[devind].pd_bar_nr++;
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assert(dev_bar_nr < BAR_NR);
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pcidev[devind].pd_bar[dev_bar_nr].pb_flags= 0;
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pcidev[devind].pd_bar[dev_bar_nr].pb_base= bar;
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pcidev[devind].pd_bar[dev_bar_nr].pb_size= bar2;
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@ -1206,7 +1254,7 @@ PRIVATE void complete_bridges()
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pci_attr_w8(devind, PPB_SUBORDBN, freebus);
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printf("CR = 0x%x\n", pci_attr_r16(devind, PCI_CR));
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printf("SECBLT = 0x%x\n", pci_attr_r8(devind, PPB_SECBLT));
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printf("SECBLT = 0x%x\n", pci_attr_r8_u(devind, PPB_SECBLT));
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printf("BRIDGECTRL = 0x%x\n",
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pci_attr_r16(devind, PPB_BRIDGECTRL));
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}
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@ -1367,7 +1415,7 @@ PRIVATE void complete_bars()
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memgap_high= base;
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bar_nr= pcidev[i].pd_bar[j].pb_nr;
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reg= PCI_BAR + 4*bar_nr;
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v32= pci_attr_r32(i, reg);
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v32= pci_attr_r32_u(i, reg);
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pci_attr_w32(i, reg, v32 | base);
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if (debug)
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{
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@ -1403,7 +1451,7 @@ PRIVATE void complete_bars()
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iogap_high= base;
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bar_nr= pcidev[i].pd_bar[j].pb_nr;
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reg= PCI_BAR + 4*bar_nr;
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v32= pci_attr_r32(i, reg);
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v32= pci_attr_r32_u(i, reg);
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pci_attr_w32(i, reg, v32 | base);
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if (debug)
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{
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@ -1645,7 +1693,7 @@ int busind;
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type= pci_pcibridge[i].type;
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if (pci_pcibridge[i].vid == 0)
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{
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headt= pci_attr_r8(devind, PCI_HEADT);
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headt= pci_attr_r8_u(devind, PCI_HEADT);
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type= 0;
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if ((headt & PHT_MASK) == PHT_BRIDGE)
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type= PCI_PPB_STD;
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@ -1659,9 +1707,9 @@ int busind;
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continue; /* Not a bridge */
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}
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baseclass= pci_attr_r8(devind, PCI_BCR);
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subclass= pci_attr_r8(devind, PCI_SCR);
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infclass= pci_attr_r8(devind, PCI_PIFR);
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baseclass= pci_attr_r8_u(devind, PCI_BCR);
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subclass= pci_attr_r8_u(devind, PCI_SCR);
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infclass= pci_attr_r8_u(devind, PCI_PIFR);
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t3= ((baseclass << 16) | (subclass << 8) | infclass);
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if (type == PCI_PPB_STD &&
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t3 != PCI_T3_PCI2PCI &&
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@ -1695,11 +1743,7 @@ int busind;
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/* Assume that the BIOS initialized the secondary bus
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* number.
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*/
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sbusn= pci_attr_r8(devind, PPB_SECBN);
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#if DEBUG
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printf("sbusn = %d\n", sbusn);
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printf("subordn = %d\n", pci_attr_r8(devind, PPB_SUBORDBN));
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#endif
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sbusn= pci_attr_r8_u(devind, PPB_SECBN);
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if (nr_pcibus >= NR_PCIBUS)
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panic("PCI","too many PCI busses", nr_pcibus);
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@ -1735,6 +1779,12 @@ int busind;
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default:
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panic("PCI","unknown PCI-PCI bridge type", type);
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}
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if (debug)
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{
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printf(
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"bus(table) = %d, bus(sec) = %d, bus(subord) = %d\n",
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ind, sbusn, pci_attr_r8_u(devind, PPB_SUBORDBN));
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}
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if (sbusn == 0)
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{
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printf("Secondary bus number not initialized\n");
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@ -1791,7 +1841,7 @@ int devind;
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elcr= elcr1 | (elcr2 << 8);
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for (i= 0; i<4; i++)
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{
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irqrc= pci_attr_r8(devind, PIIX_PIRQRCA+i);
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irqrc= pci_attr_r8_u(devind, PIIX_PIRQRCA+i);
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if (irqrc & PIIX_IRQ_DI)
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{
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if (debug)
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@ -1842,7 +1892,7 @@ int devind;
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pcidev[xdevind].pd_inuse= 1;
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nr_pcidev++;
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levmask= pci_attr_r8(xdevind, AMD_ISABR_PCIIRQ_LEV);
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levmask= pci_attr_r8_u(xdevind, AMD_ISABR_PCIIRQ_LEV);
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pciirq= pci_attr_r16(xdevind, AMD_ISABR_PCIIRQ_ROUTE);
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for (i= 0; i<4; i++)
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{
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@ -1883,7 +1933,7 @@ int devind;
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irq= 0; /* lint */
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for (i= 0; i<4; i++)
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{
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irq= pci_attr_r8(devind, SIS_ISABR_IRQ_A+i);
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irq= pci_attr_r8_u(devind, SIS_ISABR_IRQ_A+i);
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if (irq & SIS_IRQ_DISABLED)
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{
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if (debug)
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@ -1911,7 +1961,7 @@ int devind;
|
|||
|
||||
dev= pcidev[devind].pd_dev;
|
||||
func= pcidev[devind].pd_func;
|
||||
levmask= pci_attr_r8(devind, VIA_ISABR_EL);
|
||||
levmask= pci_attr_r8_u(devind, VIA_ISABR_EL);
|
||||
irq= 0; /* lint */
|
||||
edge= 0; /* lint */
|
||||
for (i= 0; i<4; i++)
|
||||
|
|
@ -1920,19 +1970,19 @@ int devind;
|
|||
{
|
||||
case 0:
|
||||
edge= (levmask & VIA_ISABR_EL_INTA);
|
||||
irq= pci_attr_r8(devind, VIA_ISABR_IRQ_R2) >> 4;
|
||||
irq= pci_attr_r8_u(devind, VIA_ISABR_IRQ_R2) >> 4;
|
||||
break;
|
||||
case 1:
|
||||
edge= (levmask & VIA_ISABR_EL_INTB);
|
||||
irq= pci_attr_r8(devind, VIA_ISABR_IRQ_R2);
|
||||
irq= pci_attr_r8_u(devind, VIA_ISABR_IRQ_R2);
|
||||
break;
|
||||
case 2:
|
||||
edge= (levmask & VIA_ISABR_EL_INTC);
|
||||
irq= pci_attr_r8(devind, VIA_ISABR_IRQ_R3) >> 4;
|
||||
irq= pci_attr_r8_u(devind, VIA_ISABR_IRQ_R3) >> 4;
|
||||
break;
|
||||
case 3:
|
||||
edge= (levmask & VIA_ISABR_EL_INTD);
|
||||
irq= pci_attr_r8(devind, VIA_ISABR_IRQ_R1) >> 4;
|
||||
irq= pci_attr_r8_u(devind, VIA_ISABR_IRQ_R1) >> 4;
|
||||
break;
|
||||
default:
|
||||
assert(0);
|
||||
|
|
@ -2425,11 +2475,11 @@ int devind;
|
|||
if (!(status & PSR_CAPPTR))
|
||||
return;
|
||||
|
||||
capptr= (pci_attr_r8(devind, PCI_CAPPTR) & PCI_CP_MASK);
|
||||
capptr= (pci_attr_r8_u(devind, PCI_CAPPTR) & PCI_CP_MASK);
|
||||
while (capptr != 0)
|
||||
{
|
||||
type = pci_attr_r8(devind, capptr+CAP_TYPE);
|
||||
next= (pci_attr_r8(devind, capptr+CAP_NEXT) & PCI_CP_MASK);
|
||||
type = pci_attr_r8_u(devind, capptr+CAP_TYPE);
|
||||
next= (pci_attr_r8_u(devind, capptr+CAP_NEXT) & PCI_CP_MASK);
|
||||
switch(type)
|
||||
{
|
||||
case 1: str= "PCI Power Management"; break;
|
||||
|
|
@ -2444,13 +2494,15 @@ int devind;
|
|||
}
|
||||
|
||||
printf(" @0x%x (0x%08x): capability type 0x%x: %s",
|
||||
capptr, pci_attr_r32(devind, capptr), type, str);
|
||||
if (type == 0x0f)
|
||||
capptr, pci_attr_r32_u(devind, capptr), type, str);
|
||||
if (type == 0x08)
|
||||
print_hyper_cap(devind, capptr);
|
||||
else if (type == 0x0f)
|
||||
{
|
||||
subtype= (pci_attr_r8(devind, capptr+2) & 0x07);
|
||||
subtype= (pci_attr_r8_u(devind, capptr+2) & 0x07);
|
||||
switch(subtype)
|
||||
{
|
||||
case 2: str= "Device Exclusion Vector"; break;
|
||||
case 0: str= "Device Exclusion Vector"; break;
|
||||
case 3: str= "IOMMU"; break;
|
||||
default: str= "(unknown type)"; break;
|
||||
}
|
||||
|
|
@ -2503,6 +2555,75 @@ int devind;
|
|||
return FALSE;
|
||||
}
|
||||
|
||||
/*===========================================================================*
|
||||
* print_hyper_cap *
|
||||
*===========================================================================*/
|
||||
PRIVATE void print_hyper_cap(devind, capptr)
|
||||
int devind;
|
||||
u8_t capptr;
|
||||
{
|
||||
u32_t v;
|
||||
u16_t cmd;
|
||||
int type0, type1;
|
||||
|
||||
printf("\n");
|
||||
v= pci_attr_r32_u(devind, capptr);
|
||||
printf("print_hyper_cap: @0x%x, off 0 (cap):", capptr);
|
||||
cmd= (v >> 16) & 0xffff;
|
||||
#if 0
|
||||
if (v & 0x10000)
|
||||
{
|
||||
printf(" WarmReset");
|
||||
v &= ~0x10000;
|
||||
}
|
||||
if (v & 0x20000)
|
||||
{
|
||||
printf(" DblEnded");
|
||||
v &= ~0x20000;
|
||||
}
|
||||
printf(" DevNum %d", (v & 0x7C0000) >> 18);
|
||||
v &= ~0x7C0000;
|
||||
#endif
|
||||
type0= (cmd & 0xE000) >> 13;
|
||||
type1= (cmd & 0xF800) >> 11;
|
||||
if (type0 == 0 || type0 == 1)
|
||||
{
|
||||
printf("Capability Type: %s\n",
|
||||
type0 == 0 ? "Slave or Primary Interface" :
|
||||
"Host or Secondary Interface");
|
||||
cmd &= ~0xE000;
|
||||
}
|
||||
else
|
||||
{
|
||||
printf(" Capability Type 0x%x", type1);
|
||||
cmd &= ~0xF800;
|
||||
}
|
||||
if (cmd)
|
||||
printf(" undecoded 0x%x\n", cmd);
|
||||
|
||||
#if 0
|
||||
printf("print_hyper_cap: off 4 (ctl): 0x%x\n",
|
||||
pci_attr_r32_u(devind, capptr+4));
|
||||
printf("print_hyper_cap: off 8 (freq/rev): 0x%x\n",
|
||||
pci_attr_r32_u(devind, capptr+8));
|
||||
printf("print_hyper_cap: off 12 (cap): 0x%x\n",
|
||||
pci_attr_r32_u(devind, capptr+12));
|
||||
printf("print_hyper_cap: off 16 (buf count): 0x%x\n",
|
||||
pci_attr_r32_u(devind, capptr+16));
|
||||
v= pci_attr_r32_u(devind, capptr+20);
|
||||
printf("print_hyper_cap: @0x%x, off 20 (bus nr): ",
|
||||
capptr+20);
|
||||
printf("prim %d", v & 0xff);
|
||||
printf(", sec %d", (v >> 8) & 0xff);
|
||||
printf(", sub %d", (v >> 16) & 0xff);
|
||||
if (v >> 24)
|
||||
printf(", reserved %d", (v >> 24) & 0xff);
|
||||
printf("\n");
|
||||
printf("print_hyper_cap: off 24 (type): 0x%x\n",
|
||||
pci_attr_r32_u(devind, capptr+24));
|
||||
#endif
|
||||
}
|
||||
|
||||
/*
|
||||
* $PchId: pci.c,v 1.7 2003/08/07 09:06:51 philip Exp $
|
||||
*/
|
||||
|
|
|
|||
Loading…
Reference in a new issue