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arm:vm header cleanup.

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Kees Jongenburger 2013-05-16 10:11:12 +02:00 committed by Kees Jongenburger
parent b9cb8251bc
commit a3f6529ee2
3 changed files with 49 additions and 19 deletions
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56
include/arch/earm/include/vm.h
View file

@ -4,26 +4,52 @@
arm/vm.h
*/
/*
* We are using the following setup
* the system is configured to have the TRE (Tex remap enable bit) set to 0
* The TEX[2:0] B and C bits are used to determins memoryt attributes.
* These bits together with the S Bit (Shareability Bit) determins the
* memory attributes.
*
* The S bit is ignored when the other attribute define the memory as
* "device" or "strongly ordered"
*
* We are setting the tex[2] bit to one to en up with the following
* encoding
*
* 00 00 Non cacheable
* 01 01 Write back, Write allocate
* 10 10 Write trough, No write allocate
* 11 11 Write back , Write alloc
*/
#define ARM_PAGE_SIZE 4096 /* small page on ARM */
#define ARM_SECTION_SIZE (1024 * 1024) /* 1 MB section */
/* Page table specific flags. */
/* Second level page table entries */
#define ARM_VM_PAGETABLE (1 << 1) /* Page table */
#define ARM_VM_PTE_PRESENT (1 << 1) /* Page is present */
#define ARM_VM_PTE_BUFFERABLE (1 << 2) /* Bufferable */
#define ARM_VM_PTE_CACHEABLE (1 << 3) /* Cacheable */
#define ARM_VM_PTE_B (1 << 2) /* B bit */
#define ARM_VM_PTE_C (1 << 3) /* C bit */
#define ARM_VM_PTE_SUPER (0x1 << 4) /* Super access only AP[1:0] */
#define ARM_VM_PTE_USER (0x3 << 4) /* Super/User access AP[1:0] */
#define ARM_VM_PTE_TEX0 (1 << 6) /* TEX[0] */
#define ARM_VM_PTE_TEX1 (1 << 7) /* TEX[1] */
#define ARM_VM_PTE_TEX2 (1 << 8) /* TEX[2] */
#define ARM_VM_PTE_RO (1 << 9) /* Read only access AP[2] */
#define ARM_VM_PTE_RW (0 << 9) /* Read-write access AP[2] */
#define ARM_VM_PTE_SHAREABLE (1 << 10) /* Shareable */
#define ARM_VM_PTE_S (1 << 10) /* "Shareable" */
#define ARM_VM_PTE_NOTGLOBAL (1 << 11) /* Not Global */
/* inner and outer write-back, write-allocate */
#define ARM_VM_PTE_WB ((0x5 << 6) | ARM_VM_PTE_BUFFERABLE)
#define ARM_VM_PTE_WB (ARM_VM_PTE_TEX2 | ARM_VM_PTE_TEX0 | ARM_VM_PTE_B)
/* inner and outer write-through, no write-allocate */
#define ARM_VM_PTE_WT ((0x6 << 6) | ARM_VM_PTE_CACHEABLE)
#define ARM_VM_PTE_WT (ARM_VM_PTE_TEX2 | ARM_VM_PTE_TEX1 | ARM_VM_PTE_C)
/* shareable device */
#define ARM_VM_PTE_DEVICE (ARM_VM_PTE_BUFFERABLE)
#define ARM_VM_PTE_DEVICE (ARM_VM_PTE_B)
#define ARM_VM_ADDR_MASK 0xFFFFF000 /* physical address */
#define ARM_VM_ADDR_MASK_1MB 0xFFF00000 /* physical address */
@ -32,20 +58,24 @@ arm/vm.h
/* Big page (1MB section) specific flags. */
#define ARM_VM_SECTION (1 << 1) /* 1MB section */
#define ARM_VM_SECTION_PRESENT (1 << 1) /* Section is present */
#define ARM_VM_SECTION_BUFFERABLE (1 << 2) /* Bufferable */
#define ARM_VM_SECTION_CACHEABLE (1 << 3) /* Cacheable */
#define ARM_VM_SECTION_B (1 << 2) /* B Bit */
#define ARM_VM_SECTION_C (1 << 3) /* C Bit */
#define ARM_VM_SECTION_DOMAIN (0xF << 5) /* Domain Number */
#define ARM_VM_SECTION_SUPER (0x1 << 10) /* Super access only AP[1:0] */
#define ARM_VM_SECTION_USER (0x3 << 10) /* Super/User access AP[1:0] */
#define ARM_VM_SECTION_TEX0 (1 << 12) /* TEX[0] */
#define ARM_VM_SECTION_TEX1 (1 << 13) /* TEX[1] */
#define ARM_VM_SECTION_TEX2 (1 << 14) /* TEX[2] */
#define ARM_VM_SECTION_RO (1 << 15) /* Read only access AP[2] */
#define ARM_VM_SECTION_SHAREABLE (1 << 16) /* Shareable */
#define ARM_VM_SECTION_NOTGLOBAL (1 << 17) /* Not Global */
/* inner and outer write-back, write-allocate */
#define ARM_VM_SECTION_WB ((0x5 << 12) | ARM_VM_SECTION_BUFFERABLE)
#define ARM_VM_SECTION_WB (ARM_VM_SECTION_TEX2 | ARM_VM_SECTION_TEX0 | ARM_VM_SECTION_B)
/* inner and outer write-through, no write-allocate */
#define ARM_VM_SECTION_WT ((0x6 << 12) | ARM_VM_SECTION_CACHEABLE)
#define ARM_VM_SECTION_WT (ARM_VM_SECTION_TEX2 | ARM_VM_SECTION_TEX1 | ARM_VM_SECTION_C)
/* shareable device */
#define ARM_VM_SECTION_DEVICE (ARM_VM_SECTION_BUFFERABLE)
#define ARM_VM_SECTION_DEVICE (ARM_VM_SECTION_B)
/* Page directory specific flags. */
#define ARM_VM_PAGEDIR (1 << 0) /* Page directory */
@ -60,7 +90,7 @@ arm/vm.h
#define ARM_VM_PT_ENT_MASK 0xFF /* Mask to get entry in page table */
#define ARM_VM_PT_ENTRIES 256 /* Number of entries in a page table */
/* ARM paging 'functions' */
#define ARM_VM_PTE(v) (((v) >> ARM_VM_PT_ENT_SHIFT) & ARM_VM_PT_ENT_MASK)
#define ARM_VM_PDE(v) ( (v) >> ARM_VM_DIR_ENT_SHIFT)
#define ARM_VM_PFA(e) ( (e) & ARM_VM_ADDR_MASK)

2
servers/vm/arch/earm/pagetable.h
View file

@ -16,7 +16,7 @@
#define PTF_NOCACHE ARM_VM_PTE_DEVICE
#define PTF_CACHEWB ARM_VM_PTE_WB
#define PTF_CACHEWT ARM_VM_PTE_WT
#define PTF_SHARE ARM_VM_PTE_SHAREABLE
#define PTF_SHARE ARM_VM_PTE_S
#define ARCH_VM_DIR_ENTRIES ARM_VM_DIR_ENTRIES
#define ARCH_BIG_PAGE_SIZE ARM_SECTION_SIZE

6
servers/vm/arch/i386/pagetable.c
View file

@ -409,7 +409,7 @@ void vm_pagelock(void *vir, int lockflag)
#if defined(__arm__)
else
flags |= ARCH_VM_PTE_RO;
flags |= ARM_VM_PTE_WB | ARM_VM_PTE_SHAREABLE; // LSC FIXME
flags |= ARM_VM_PTE_WB | ARM_VM_PTE_S ; // LSC FIXME
#endif
/* Update flags. */
@ -598,7 +598,7 @@ static char *ptestr(u32_t pte)
FLAG(I386_VM_PTAVAIL3, "AV3");
#elif defined(__arm__)
FLAG(ARM_VM_PTE_SUPER, "S");
FLAG(ARM_VM_PTE_SHAREABLE, "SH");
FLAG(ARM_VM_PTE_S, "SH");
FLAG(ARM_VM_PTE_WB, "WB");
FLAG(ARM_VM_PTE_WT, "WT");
#endif
@ -689,7 +689,7 @@ int pt_ptmap(struct vmproc *src_vmp, struct vmproc *dst_vmp)
#elif defined(__arm__)
if((r=pt_writemap(dst_vmp, &dst_vmp->vm_pt, viraddr, physaddr, ARCH_PAGEDIR_SIZE,
ARCH_VM_PTE_PRESENT | ARCH_VM_PTE_USER |
ARM_VM_PTE_WB | ARM_VM_PTE_SHAREABLE, //LSC FIXME
ARM_VM_PTE_WB | ARM_VM_PTE_S, //LSC FIXME
#endif
WMF_OVERWRITE)) != OK) {
return r;