<vmparam.h>
Change-Id: I941ea3111703ed089bfdaf87d26158ab8697a80d
This commit is contained in:
Ben Gras
Lionel Sambuc
parent
5cecdfcb3e
commit
81473dbba0
6 changed files with 517 additions and 8 deletions
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@ -2,6 +2,7 @@
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getpagesize.c
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*/
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#include <sys/cdefs.h>
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#include <sys/types.h>
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#include "namespace.h"
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#include <machine/vmparam.h>
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@ -2,6 +2,6 @@
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INCSDIR= /usr/include/arm/arm32
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INCS= param.h types.h vmparam.h
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INCS= param.h types.h vmparam.h pte.h
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.include <bsd.kinc.mk>
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337
sys/arch/arm/include/arm32/pte.h
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337
sys/arch/arm/include/arm32/pte.h
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@ -0,0 +1,337 @@
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/* $NetBSD: pte.h,v 1.13 2012/09/11 15:28:14 matt Exp $ */
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/*
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* Copyright (c) 2001, 2002 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Jason R. Thorpe for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
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||||
* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _ARM_PTE_H_
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#define _ARM_PTE_H_
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/*
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* The ARM MMU architecture was introduced with ARM v3 (previous ARM
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* architecture versions used an optional off-CPU memory controller
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* to perform address translation).
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*
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* The ARM MMU consists of a TLB and translation table walking logic.
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* There is typically one TLB per memory interface (or, put another
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* way, one TLB per software-visible cache).
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*
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* The ARM MMU is capable of mapping memory in the following chunks:
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*
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* 16M SuperSections (L1 table, ARMv6+)
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*
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* 1M Sections (L1 table)
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*
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* 64K Large Pages (L2 table)
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*
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* 4K Small Pages (L2 table)
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*
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* 1K Tiny Pages (L2 table)
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*
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* There are two types of L2 tables: Coarse Tables and Fine Tables (not
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* available on ARMv6+). Coarse Tables can map Large and Small Pages.
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* Fine Tables can map Tiny Pages.
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*
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* Coarse Tables can define 4 Subpages within Large and Small pages.
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* Subpages define different permissions for each Subpage within
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* a Page. ARMv6 format Coarse Tables have no subpages.
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*
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* Coarse Tables are 1K in length. Fine tables are 4K in length.
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*
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* The Translation Table Base register holds the pointer to the
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* L1 Table. The L1 Table is a 16K contiguous chunk of memory
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* aligned to a 16K boundary. Each entry in the L1 Table maps
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* 1M of virtual address space, either via a Section mapping or
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* via an L2 Table.
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*
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* ARMv6+ has a second TTBR register which can be used if any of the
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* upper address bits are non-zero (think kernel). For NetBSD, this
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* would be 1 upper bit splitting user/kernel in a 2GB/2GB split.
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* This would also reduce the size of the L1 Table to 8K.
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*
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* In addition, the Fast Context Switching Extension (FCSE) is available
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* on some ARM v4 and ARM v5 processors. FCSE is a way of eliminating
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* TLB/cache flushes on context switch by use of a smaller address space
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* and a "process ID" that modifies the virtual address before being
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* presented to the translation logic.
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*/
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#ifndef _LOCORE
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typedef uint32_t pd_entry_t; /* L1 table entry */
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typedef uint32_t pt_entry_t; /* L2 table entry */
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#endif /* _LOCORE */
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#define L1_SS_SIZE 0x01000000 /* 16M */
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#define L1_SS_OFFSET (L1_SS_SIZE - 1)
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#define L1_SS_FRAME (~L1_SS_OFFSET)
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#define L1_SS_SHIFT 24
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#define L1_S_SIZE 0x00100000 /* 1M */
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#define L1_S_OFFSET (L1_S_SIZE - 1)
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#define L1_S_FRAME (~L1_S_OFFSET)
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#define L1_S_SHIFT 20
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#define L2_L_SIZE 0x00010000 /* 64K */
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#define L2_L_OFFSET (L2_L_SIZE - 1)
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#define L2_L_FRAME (~L2_L_OFFSET)
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#define L2_L_SHIFT 16
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#define L2_S_SEGSIZE (PAGE_SIZE * L2_S_SIZE / 4)
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#define L2_S_SIZE 0x00001000 /* 4K */
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#define L2_S_OFFSET (L2_S_SIZE - 1)
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#define L2_S_FRAME (~L2_S_OFFSET)
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#define L2_S_SHIFT 12
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#define L2_T_SIZE 0x00000400 /* 1K */
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#define L2_T_OFFSET (L2_T_SIZE - 1)
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#define L2_T_FRAME (~L2_T_OFFSET)
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#define L2_T_SHIFT 10
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/*
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* The NetBSD VM implementation only works on whole pages (4K),
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* whereas the ARM MMU's Coarse tables are sized in terms of 1K
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* (16K L1 table, 1K L2 table).
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*
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* So, we allocate L2 tables 4 at a time, thus yielding a 4K L2
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* table.
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*/
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#define L1_ADDR_BITS 0xfff00000 /* L1 PTE address bits */
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#define L2_ADDR_BITS 0x000ff000 /* L2 PTE address bits */
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#define L1_TABLE_SIZE 0x4000 /* 16K */
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#define L2_TABLE_SIZE 0x1000 /* 4K */
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/*
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* The new pmap deals with the 1KB coarse L2 tables by
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* allocating them from a pool. Until every port has been converted,
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* keep the old L2_TABLE_SIZE define lying around. Converted ports
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* should use L2_TABLE_SIZE_REAL until then.
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*/
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#define L2_TABLE_SIZE_REAL 0x400 /* 1K */
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/*
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* ARM L1 Descriptors
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*/
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#define L1_TYPE_INV 0x00 /* Invalid (fault) */
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#define L1_TYPE_C 0x01 /* Coarse L2 */
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#define L1_TYPE_S 0x02 /* Section */
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#define L1_TYPE_F 0x03 /* Fine L2 */
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#define L1_TYPE_MASK 0x03 /* mask of type bits */
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/* L1 Section Descriptor */
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#define L1_S_B 0x00000004 /* bufferable Section */
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#define L1_S_C 0x00000008 /* cacheable Section */
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#define L1_S_IMP 0x00000010 /* implementation defined */
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#define L1_S_DOM(x) ((x) << 5) /* domain */
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#define L1_S_DOM_MASK L1_S_DOM(0xf)
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#define L1_S_AP(x) ((x) << 10) /* access permissions */
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#define L1_S_ADDR_MASK 0xfff00000 /* phys address of section */
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#define L1_S_XSCALE_P 0x00000200 /* ECC enable for this section */
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#define L1_S_XS_TEX(x) ((x) << 12) /* Type Extension */
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#define L1_S_V6_TEX(x) L1_S_XS_TEX(x)
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#define L1_S_V6_P 0x00000200 /* ECC enable for this section */
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#define L1_S_V6_SUPER 0x00040000 /* ARMv6 SuperSection (16MB) bit */
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#define L1_S_V6_XN L1_S_IMP /* ARMv6 eXecute Never */
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#define L1_S_V6_APX 0x00008000 /* ARMv6 AP eXtension */
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#define L1_S_V6_S 0x00010000 /* ARMv6 Shared */
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#define L1_S_V6_nG 0x00020000 /* ARMv6 not-Global */
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#define L1_S_V6_SS 0x00040000 /* ARMv6 SuperSection */
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#define L1_S_V6_NS 0x00080000 /* ARMv6 Not Secure */
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/* L1 Coarse Descriptor */
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#define L1_C_IMP0 0x00000004 /* implementation defined */
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#define L1_C_IMP1 0x00000008 /* implementation defined */
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#define L1_C_IMP2 0x00000010 /* implementation defined */
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#define L1_C_DOM(x) ((x) << 5) /* domain */
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#define L1_C_DOM_MASK L1_C_DOM(0xf)
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#define L1_C_ADDR_MASK 0xfffffc00 /* phys address of L2 Table */
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#define L1_C_XSCALE_P 0x00000200 /* ECC enable for this section */
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#define L1_C_V6_P 0x00000200 /* ECC enable for this section */
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/* L1 Fine Descriptor */
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#define L1_F_IMP0 0x00000004 /* implementation defined */
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#define L1_F_IMP1 0x00000008 /* implementation defined */
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#define L1_F_IMP2 0x00000010 /* implementation defined */
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#define L1_F_DOM(x) ((x) << 5) /* domain */
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#define L1_F_DOM_MASK L1_F_DOM(0xf)
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#define L1_F_ADDR_MASK 0xfffff000 /* phys address of L2 Table */
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#define L1_F_XSCALE_P 0x00000200 /* ECC enable for this section */
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/*
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* ARM L2 Descriptors
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*/
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#define L2_TYPE_INV 0x00 /* Invalid (fault) */
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#define L2_TYPE_L 0x01 /* Large Page */
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#define L2_TYPE_S 0x02 /* Small Page */
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#define L2_TYPE_T 0x03 /* Tiny Page (not armv7) */
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#define L2_TYPE_MASK 0x03 /* mask of type bits */
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/*
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* This L2 Descriptor type is available on XScale processors
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* when using a Coarse L1 Descriptor. The Extended Small
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* Descriptor has the same format as the XScale Tiny Descriptor,
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* but describes a 4K page, rather than a 1K page.
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* For V6 MMU, this is used when XP bit is cleared.
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*/
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#define L2_TYPE_XS 0x03 /* XScale/ARMv6 Extended Small Page */
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#define L2_B 0x00000004 /* Bufferable page */
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#define L2_C 0x00000008 /* Cacheable page */
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#define L2_AP0(x) ((x) << 4) /* access permissions (sp 0) */
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#define L2_AP1(x) ((x) << 6) /* access permissions (sp 1) */
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#define L2_AP2(x) ((x) << 8) /* access permissions (sp 2) */
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#define L2_AP3(x) ((x) << 10) /* access permissions (sp 3) */
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#define L2_AP(x) (L2_AP0(x) | L2_AP1(x) | L2_AP2(x) | L2_AP3(x))
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#define L2_XS_L_TEX(x) ((x) << 12) /* Type Extension */
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#define L2_XS_T_TEX(x) ((x) << 6) /* Type Extension */
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#define L2_XS_XN 0x00000001 /* ARMv6 eXecute Never (when XP=1) */
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#define L2_XS_APX 0x00000200 /* ARMv6 AP eXtension */
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#define L2_XS_S 0x00000400 /* ARMv6 Shared */
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#define L2_XS_nG 0x00000800 /* ARMv6 Not-Global */
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#define L2_V6_L_TEX L2_XS_L_TEX
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#define L2_V6_XS_TEX L2_XS_T_TEX
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/*
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* Access Permissions for L1 and L2 Descriptors.
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*/
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#define AP_W 0x01 /* writable */
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#define AP_U 0x02 /* user */
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/*
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* Access Permissions for L1 and L2 of ARMv6 with XP=1 and ARMv7
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*/
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#define AP_R 0x01 /* readable */
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#define AP_RO 0x20 /* read-only */
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/*
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* Short-hand for common AP_* constants.
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*
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* Note: These values assume the S (System) bit is set and
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* the R (ROM) bit is clear in CP15 register 1.
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*/
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#define AP_KR 0x00 /* kernel read */
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#define AP_KRW 0x01 /* kernel read/write */
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#define AP_KRWUR 0x02 /* kernel read/write usr read */
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#define AP_KRWURW 0x03 /* kernel read/write usr read/write */
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/*
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* Note: These values assume the S (System) and the R (ROM) bits are clear and
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* the XP (eXtended page table) bit is set in CP15 register 1. ARMv6 only.
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*/
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#define APX_KR(APX) (APX|0x01) /* kernel read */
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#define APX_KRUR(APX) (APX|0x02) /* kernel read user read */
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#define APX_KRW(APX) ( 0x01) /* kernel read/write */
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#define APX_KRWUR(APX) ( 0x02) /* kernel read/write user read */
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#define APX_KRWURW(APX) ( 0x03) /* kernel read/write user read/write */
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/*
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* Note: These values are for the simplified access permissions model
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* of ARMv7. Assumes that AFE is clear in CP15 register 1.
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* Also used for ARMv6 with XP bit set.
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*/
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#define AP7_KR 0x21 /* kernel read */
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#define AP7_KRUR 0x23 /* kernel read usr read */
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#define AP7_KRW 0x01 /* kernel read/write */
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#define AP7_KRWURW 0x03 /* kernel read/write usr read/write */
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/*
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* Domain Types for the Domain Access Control Register.
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*/
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#define DOMAIN_FAULT 0x00 /* no access */
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#define DOMAIN_CLIENT 0x01 /* client */
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#define DOMAIN_RESERVED 0x02 /* reserved */
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#define DOMAIN_MANAGER 0x03 /* manager */
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/*
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* Type Extension bits for XScale processors.
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*
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* Behavior of C and B when X == 0:
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*
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* C B Cacheable Bufferable Write Policy Line Allocate Policy
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* 0 0 N N - -
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* 0 1 N Y - -
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* 1 0 Y Y Write-through Read Allocate
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* 1 1 Y Y Write-back Read Allocate
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*
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* Behavior of C and B when X == 1:
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* C B Cacheable Bufferable Write Policy Line Allocate Policy
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* 0 0 - - - - DO NOT USE
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* 0 1 N Y - -
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* 1 0 Mini-Data - - -
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* 1 1 Y Y Write-back R/W Allocate
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*/
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#define TEX_XSCALE_X 0x01 /* X modifies C and B */
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/*
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* Type Extension bits for ARM V6 and V7 MMU
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*
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* TEX C B Shared
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* 000 0 0 Strong order yes
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* 000 0 1 Shared device yes
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* 000 1 0 write through, no write alloc S-bit
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* 000 1 1 write back, no write alloc S-bit
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* 001 0 0 non-cacheable S-bit
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* 001 0 1 reserved
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* 001 1 0 reserved
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* 001 1 1 write back, write alloc S-bit
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* 010 0 0 Non-shared device no
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* 010 0 1 reserved
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* 010 1 X reserved
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* 011 X X reserved
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* 1BB A A BB for internal, AA for external S-bit
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*
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* BB internal cache
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* 0 0 Non-cacheable non-buffered
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* 0 1 Write back, write alloc, buffered
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* 1 0 Write through, no write alloc, buffered
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* (non-cacheable for MPCore)
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* 1 1 Write back, no write alloc, buffered
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* (write back, write alloc for MPCore)
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*
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* AA external cache
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* 0 0 Non-cacheable non-buffered
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* 0 1 Write back, write alloc, buffered
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* 1 0 Write through, no write alloc, buffered
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* 1 1 Write back, no write alloc, buffered
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*/
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#define TEX_ARMV6_TEX 0x07 /* 3 bits in TEX */
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#endif /* _ARM_PTE_H_ */
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@ -1,12 +1,103 @@
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/* $NetBSD: vmparam.h,v 1.27 2012/08/16 07:25:37 matt Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2001, 2002 Wasabi Systems, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Written by Jason R. Thorpe for Wasabi Systems, Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed for the NetBSD Project by
|
||||
* Wasabi Systems, Inc.
|
||||
* 4. The name of Wasabi Systems, Inc. may not be used to endorse
|
||||
* or promote products derived from this software without specific prior
|
||||
* written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _ARM_ARM32_VMPARAM_H_
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||||
#define _ARM_ARM32_VMPARAM_H_
|
||||
#define _ARM_ARM32_VMPARAM_H_
|
||||
|
||||
#if defined(_KERNEL) || defined(_KMEMUSER) || defined(__minix)
|
||||
|
||||
/*
|
||||
* Virtual Memory parameters common to all arm32 platforms.
|
||||
*/
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
#include <sys/simplelock.h> /* struct simplelock */
|
||||
#endif /* __ASSEMBLER__ */
|
||||
#include <arm/arm32/pte.h> /* pt_entry_t */
|
||||
|
||||
#define USRSTACK VM_MAXUSER_ADDRESS
|
||||
|
||||
/*
|
||||
* Note that MAXTSIZ can't be larger than 32M, otherwise the compiler
|
||||
* would have to be changed to not generate "bl" instructions.
|
||||
*/
|
||||
#define MAXTSIZ (16*1024*1024) /* max text size */
|
||||
#ifndef DFLDSIZ
|
||||
#define DFLDSIZ (128*1024*1024) /* initial data size limit */
|
||||
#endif
|
||||
#ifndef MAXDSIZ
|
||||
#define MAXDSIZ (512*1024*1024) /* max data size */
|
||||
#endif
|
||||
#ifndef DFLSSIZ
|
||||
#define DFLSSIZ (2*1024*1024) /* initial stack size limit */
|
||||
#endif
|
||||
#ifndef MAXSSIZ
|
||||
#define MAXSSIZ (8*1024*1024) /* max stack size */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* While the ARM architecture defines Section mappings, large pages,
|
||||
* and small pages, the standard page size is (and will always be) 4K.
|
||||
*/
|
||||
#define PAGE_SHIFT 12
|
||||
#define PAGE_SIZE (1 << PAGE_SHIFT)
|
||||
#define PAGE_MASK (PAGE_SIZE - 1)
|
||||
|
||||
/*
|
||||
* Mach derived constants
|
||||
*/
|
||||
#define VM_MIN_ADDRESS ((vaddr_t) 0x00001000)
|
||||
#define VM_MAXUSER_ADDRESS ((vaddr_t) KERNEL_BASE - 0x1000)
|
||||
#define VM_MAX_ADDRESS VM_MAXUSER_ADDRESS
|
||||
|
||||
#define VM_MIN_KERNEL_ADDRESS ((vaddr_t) KERNEL_BASE)
|
||||
#define VM_MAX_KERNEL_ADDRESS ((vaddr_t) 0xffffefff)
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
/* XXX max. amount of KVM to be used by buffers. */
|
||||
#ifndef VM_MAX_KERNEL_BUF
|
||||
extern vaddr_t virtual_avail;
|
||||
extern vaddr_t virtual_end;
|
||||
|
||||
#define VM_MAX_KERNEL_BUF \
|
||||
((virtual_end - virtual_avail) * 4 / 10)
|
||||
#endif
|
||||
#endif /* __ASSEMBLER__ */
|
||||
|
||||
#endif /* _KERNEL || _KMEMUSER */
|
||||
|
||||
#endif /* _ARM_ARM32_VMPARAM_H_ */
|
||||
|
|
|
|||
|
|
@ -32,11 +32,7 @@
|
|||
#ifndef _EVBARM_VMPARAM_H_
|
||||
#define _EVBARM_VMPARAM_H_
|
||||
|
||||
#if defined(__minix)
|
||||
#include <arm/arm32/vmparam.h>
|
||||
#endif /* defined(__minix) */
|
||||
|
||||
#if defined(_KERNEL) || defined(_KMEMUSER)
|
||||
#if defined(_KERNEL) || defined(_KMEMUSER) || defined(__minix)
|
||||
|
||||
#include <arm/arm32/vmparam.h>
|
||||
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: vmparam.h,v 1.72 2010/11/14 13:33:21 uebayasi Exp $ */
|
||||
/* $NetBSD: vmparam.h,v 1.75 2012/08/15 08:10:28 sborrill Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 1990 The Regents of the University of California.
|
||||
|
|
@ -37,6 +37,9 @@
|
|||
#ifndef _I386_VMPARAM_H_
|
||||
#define _I386_VMPARAM_H_
|
||||
|
||||
#include <sys/tree.h>
|
||||
#include <sys/mutex.h>
|
||||
|
||||
/*
|
||||
* Machine dependent constants for 386.
|
||||
*/
|
||||
|
|
@ -49,4 +52,85 @@
|
|||
#define PAGE_SIZE (1 << PAGE_SHIFT)
|
||||
#define PAGE_MASK (PAGE_SIZE - 1)
|
||||
|
||||
/*
|
||||
* Virtual address space arrangement. On 386, both user and kernel
|
||||
* share the address space, not unlike the vax.
|
||||
* USRSTACK is the top (end) of the user stack. Immediately above the
|
||||
* user stack is the page table map, and then kernel address space.
|
||||
*/
|
||||
#define USRSTACK VM_MAXUSER_ADDRESS
|
||||
|
||||
/*
|
||||
* Virtual memory related constants, all in bytes
|
||||
*/
|
||||
#define MAXTSIZ (256*1024*1024) /* max text size */
|
||||
#ifndef DFLDSIZ
|
||||
#define DFLDSIZ (256*1024*1024) /* initial data size limit */
|
||||
#endif
|
||||
#ifndef MAXDSIZ
|
||||
#define MAXDSIZ (3U*1024*1024*1024) /* max data size */
|
||||
#endif
|
||||
#ifndef DFLSSIZ
|
||||
#define DFLSSIZ (2*1024*1024) /* initial stack size limit */
|
||||
#endif
|
||||
#ifndef MAXSSIZ
|
||||
#define MAXSSIZ (64*1024*1024) /* max stack size */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* IA-32 can't do per-page execute permission, so instead we implement
|
||||
* two executable segments for %cs, one that covers everything and one
|
||||
* that excludes some of the address space (currently just the stack).
|
||||
* I386_MAX_EXE_ADDR is the upper boundary for the smaller segment.
|
||||
*/
|
||||
#define I386_MAX_EXE_ADDR (USRSTACK - MAXSSIZ)
|
||||
|
||||
/*
|
||||
* Size of User Raw I/O map
|
||||
*/
|
||||
#define USRIOSIZE 300
|
||||
|
||||
/*
|
||||
* Mach derived constants
|
||||
*/
|
||||
|
||||
/* user/kernel map constants */
|
||||
#define VM_MIN_ADDRESS ((vaddr_t)0)
|
||||
#define VM_MAXUSER_ADDRESS ((vaddr_t)(PDIR_SLOT_PTE << L2_SHIFT))
|
||||
#define VM_MAX_ADDRESS \
|
||||
((vaddr_t)((PDIR_SLOT_PTE << L2_SHIFT) + (PDIR_SLOT_PTE << L1_SHIFT)))
|
||||
#define VM_MIN_KERNEL_ADDRESS ((vaddr_t)(PDIR_SLOT_KERN << L2_SHIFT))
|
||||
#define VM_MAX_KERNEL_ADDRESS ((vaddr_t)((PDIR_SLOT_KERN + NKL2_MAX_ENTRIES) << L2_SHIFT))
|
||||
|
||||
/*
|
||||
* The address to which unspecified mapping requests default
|
||||
*/
|
||||
#ifdef _KERNEL_OPT
|
||||
#include "opt_uvm.h"
|
||||
#include "opt_xen.h"
|
||||
#endif
|
||||
#define __USE_TOPDOWN_VM
|
||||
#define VM_DEFAULT_ADDRESS(da, sz) \
|
||||
trunc_page(USRSTACK - MAXSSIZ - (sz))
|
||||
|
||||
/* XXX max. amount of KVM to be used by buffers. */
|
||||
#ifndef VM_MAX_KERNEL_BUF
|
||||
#define VM_MAX_KERNEL_BUF (384 * 1024 * 1024)
|
||||
#endif
|
||||
|
||||
/* virtual sizes (bytes) for various kernel submaps */
|
||||
#define VM_PHYS_SIZE (USRIOSIZE*PAGE_SIZE)
|
||||
|
||||
#define VM_PHYSSEG_STRAT VM_PSTRAT_BIGFIRST
|
||||
|
||||
#ifdef XEN
|
||||
#define VM_PHYSSEG_MAX 1
|
||||
#define VM_NFREELIST 1
|
||||
#else
|
||||
#define VM_PHYSSEG_MAX 16 /* 1 "hole" + 15 free lists */
|
||||
#define VM_NFREELIST 2
|
||||
#define VM_FREELIST_FIRST16 1
|
||||
#endif /* XEN */
|
||||
#define VM_FREELIST_DEFAULT 0
|
||||
|
||||
#endif /* _I386_VMPARAM_H_ */
|
||||
|
|
|
|||
Loading…
Reference in a new issue