i386 cpu.h
Change-Id: Iae6d8727ba6e005a8b6e3bed4008f3f3282a1a81
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#ifndef _IBM_CPU_H
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/* $NetBSD: cpu.h,v 1.178 2011/12/30 17:57:49 cherry Exp $ */
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#define _IBM_CPU_H 1
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#define X86_FLAG_C (1L << 0) /* S Carry */
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/*-
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#define X86_FLAG_P (1L << 2) /* S Parity */
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* Copyright (c) 1990 The Regents of the University of California.
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#define X86_FLAG_A (1L << 4) /* S Aux. carry */
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* All rights reserved.
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#define X86_FLAG_Z (1L << 6) /* S Zero */
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*
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#define X86_FLAG_S (1L << 7) /* S Sign */
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* This code is derived from software contributed to Berkeley by
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* William Jolitz.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)cpu.h 5.4 (Berkeley) 5/9/91
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*/
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#define X86_FLAG_T (1L << 8) /* X Trap */
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#ifndef _I386_CPU_H_
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#define X86_FLAG_I (1L << 9) /* X Interrupt */
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#define _I386_CPU_H_
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#define X86_FLAG_D (1L << 10) /* C Direction */
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#define X86_FLAG_O (1L << 11) /* S Overflow */
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/* User flags are S (Status) and C (Control) flags. */
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#define X86_FLAGS_USER (X86_FLAG_C | X86_FLAG_P | X86_FLAG_A | X86_FLAG_Z | \
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X86_FLAG_S | X86_FLAG_D | X86_FLAG_O)
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#include <x86/cpu.h>
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#include <x86/cpu.h>
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#ifdef _KERNEL
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#if defined(__GNUC__) && !defined(_MODULE)
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static struct cpu_info *x86_curcpu(void);
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static lwp_t *x86_curlwp(void);
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__inline static struct cpu_info * __unused
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x86_curcpu(void)
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{
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struct cpu_info *ci;
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__asm volatile("movl %%fs:%1, %0" :
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"=r" (ci) :
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"m"
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(*(struct cpu_info * const *)offsetof(struct cpu_info, ci_self)));
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return ci;
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}
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__inline static lwp_t * __attribute__ ((const))
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x86_curlwp(void)
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{
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lwp_t *l;
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__asm volatile("movl %%fs:%1, %0" :
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"=r" (l) :
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"m"
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(*(struct cpu_info * const *)offsetof(struct cpu_info, ci_curlwp)));
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return l;
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}
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__inline static void __unused
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cpu_set_curpri(int pri)
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{
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__asm volatile(
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"movl %1, %%fs:%0" :
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"=m" (*(struct cpu_info *)offsetof(struct cpu_info, ci_schedstate.spc_curpriority)) :
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"r" (pri)
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);
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}
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#endif
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#endif
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#define CLKF_USERMODE(frame) USERMODE((frame)->cf_if.if_cs, (frame)->cf_if.if_eflags)
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#define CLKF_PC(frame) ((frame)->cf_if.if_eip)
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#define CLKF_INTR(frame) (curcpu()->ci_idepth > 0)
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#define LWP_PC(l) ((l)->l_md.md_regs->tf_eip)
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#ifdef PAE
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void cpu_alloc_l3_page(struct cpu_info *);
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#endif /* PAE */
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#endif /* _KERNEL */
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#ifdef __minix
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#include <x86/psl.h>
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/* User flags are S (Status) and C (Control) flags. */
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#define X86_FLAGS_USER (PSL_C | PSL_PF | PSL_AF | PSL_Z | \
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PSL_N | PSL_D | PSL_V)
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#endif
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#endif /* !_I386_CPU_H_ */
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